Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1999-06-08
2000-10-17
Le, Vu A.
Static information storage and retrieval
Read/write circuit
Data refresh
36523006, G11C 700
Patent
active
061341681
ABSTRACT:
A counter (450) for generating a series of binary addresses, each of the addresses including a set of one or more most-significant bits. The counter includes circuitry to generate the addresses, including the set of most-significant bits (402), in a first mode and circuitry to generate the addresses (400), excluding the set of most significant bits, in a second mode. The counter is operable to transition between the first and second modes. The counter also includes circuitry to generate the addresses in the first mode in a non-binary count order in which the set of most-significant address bits is a set of least-significant bits in the count order.
REFERENCES:
patent: 4459660 (1984-07-01), Bellay et al.
patent: 5210717 (1993-05-01), Tamaki
patent: 5255378 (1993-10-01), Crawford et al.
patent: 5365487 (1994-11-01), Patel et al.
patent: 5703828 (1997-12-01), Park et al.
patent: 5835956 (1998-11-01), Park et al.
"Low Power Architecture Design and Compilation Techniques for High-Performance Processors", Su, et. al., Advanced Computer Architecture Laboratory, University of Southern California, 1994, pp. 489-498.
Eplett Steven C.
Harrington Matthew R.
Mazumder Kallol
Smith Scott E.
Donaldson Richard L.
Le Vu A.
Rountree Robert N.
Skrehot Michael K.
Texas Instruments Incorporated
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