Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2001-08-15
2004-10-19
Le, Don (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S083000, C326S026000
Reexamination Certificate
active
06806728
ABSTRACT:
FIELD OF THE INVENTION
This present invention relates to digital interface circuitry. More specifically, it relates to on-die termination (ODT) circuitry.
BACKGROUND OF THE INVENTION
Computer systems and other electronic systems typically use buses for interconnecting integrated circuit components so that the integrated circuit components can communicate with one another. System buses typically connect master devices, such as microprocessors and controllers, and slave devices, such as memories and bus transceivers.
Each master and slave device that is coupled to the bus typically includes output driver circuitry for driving signals onto the bus. Prior bus systems have employed a variety of types of logic circuitry including: transistor-transistor logic (“TTL”), emitter-coupled logical (“ECL”), complementary-metal-oxide-semiconductor (CMOS), N-channel metal oxide semiconductor (“NMOS”), P-channel metal oxide semiconductor (“PMOS”), and gunning transistor logic (“GTL”).
The different types of logic circuitry described above are generally driven by voltage level signals. For example, a logic-1 in TTL is typically represented by a voltage signal level of 5V while a logic-0 is typically represented by a voltage signal level of 0V. As supply voltage levels for digital circuits have steadily declined from 5V to approximately 1.8V, it has become advantageous, to provide buses that are driven by a current mode output driver. One benefit to a current mode driver is a reduction of peak switching current. For a voltage mode driver the output transistor of the driver must be sized to drive the maximum specified current under worst case operating conditions. Under nominal conditions with less than maximum load, the current transient when the output is switched, but before it reaches the rail, can be very large. The current mode driver, on the other hand, draws a known current regardless of load and operating conditions.
In addition, for a voltage mode driver, impedance discontinuities occur when the driving device is characterized by a low output impedance when in a sending state. These discontinuities cause reflections which dictate extra bus settling time. Current mode drivers, however, are characterized by a high output impedance so that a signal propagating on the bus encounters no significant discontinuity in line impedance due to a driver in a sending state. Thus, reflections are typically avoided and the required bus settling time is decreased.
An example of a current mode bus is disclosed in U.S. Pat. No. 4,481,625, issued Nov. 6, 1984, entitled High Speed Data Bus System. An NMOS current mode driver for a low voltage swing bus is disclosed in PCT international patent application number PCT/US91/02590 filed Apr. 16, 1991, published Oct. 31, 1991, and entitled Integrated Circuit I/O Using a High Performance Bus Interface.
One disadvantage of certain prior current mode drivers is that current sometimes varies from driver to driver. Variations can also happen over time. Temperature variations, process variations, and power supply variations sometimes cause such variations. Current variations in turn lead to voltage level variations on the bus. Bus voltage level variations can in turn lead to the erroneous reading of bus levels, which can result in the loss of data or other errors. In addition, attempts to design around these variations by raising voltage levels sometimes leads to higher power dissipations, especially in extreme cases. In any event, variations in bus voltage levels are typically more problematic for buses with low voltage swings.
FIG. 1
is a functional block diagram illustrating an example of a bus system
10
. In this example, a bus
20
provides for data transfer between a memory controller device
30
, which is the bus master for bus
20
, and RDRAMs
12
and
14
, which are slave devices on bus
20
. Bus
20
is a high speed, low voltage swing bus that typically includes a plurality of transmission lines for carrying data and control information. Each of memory controller
30
and RDRAMs
12
and
14
typically includes an interface circuit for coupling to bus
20
, such as interface driver circuit
32
for memory controller
30
. Each interface circuit typically includes a plurality of current mode drivers for driving each line of bus
20
, e.g. for each master and slave device, there is one output driver for each transmission line of bus
20
. Each of the current mode drivers accurately provides a desired current for the respective line of bus
30
.
Each of the current mode drivers typically includes a plurality of transistors coupled in parallel between a respective transmission line of the bus and a ground voltage supply rail. A logic circuit is coupled to the gates of the plurality of transistors. The widths of the transistors are typically binary multiples of one another. A current controller is coupled to the logic circuit for controlling the logic circuit in order to turn on or off a particular combination of the plurality of transistors such that a desired current draw for the line of the bus may be selected. The desired current for the line of the bus, in turn, becomes a desired voltage for the line of bus
20
. The controller typically includes a variable level circuit, a comparator, a counter, and a control logic. Once selected, the desired current is relatively independent of power supply, process, and temperature variations. U.S. Pat. No. 5,254,883 to Horowitz et al. for Electrical Current Source Circuitry for a Bus, herein incorporated by reference in its entirety for all purposes, illustrates an example of a circuit for setting a desired current draw for circuitry interfacing with a bus as well as information regarding typical bus systems such as bus system
10
.
As noted above, the modern trend for the interface drivers for bus
20
is to use current mode drivers having low voltage swing signals. The current mode drivers of interface driver
32
of memory controller
30
and RDRAMs
12
and
14
control the voltage levels of bus
20
. When a current mode driver is in an “off” state, then the respective bus line will either stay at a high voltage level or rise to the high voltage level. When the current mode driver is in an “off” state, there is approximately zero voltage drop across the line termination resistors, represented in
FIG. 1
by resistor
26
, because the current mode driver is not drawing current from the bus line. Thus, the voltage level of the bus line will rise to the termination voltage V
term
for bus
20
.
When a current mode driver is in an “on” state, then the current mode driver draws current from the respective bus line and lowers the voltage level of the bus line. In other words, when the current mode driver is in an “on” state, pull down current flows through the current driver to the ground supply rail. The low voltage level of bus
20
is, accordingly, determined by the pull down current drawn by the driver. The pull down current flows through the termination resistor
26
causing a voltage drop to appear on the respective line of bus
20
. The pull down current (flowing through the output driver and the respective termination resistor) is referred to as the desired current. The magnitude of the desired current can be set or selected by the user to allow for different bus impedance, noise immunity, and power dissipation requirements.
FIG. 5
is a voltage waveform diagram illustrating how the current adjustment performed by the circuits of
FIGS. 2 and 4
, discussed below, can affect the signal waveform generated by an output driver. In
FIG. 5
, waveform
180
illustrates a response where an output high voltage level V
OH
starts at V
TERM
(typically 1.8 V in many current RAMBUS designs) and is pulled low by the output driver to an output low voltage level V
OL
(typically 1.0 V in many current RAMBUS designs). At the output high voltage level V
OH
, the output driver circuit draws no current. At the output low voltage level V
OL
, the output driver draws sufficient current to pull the bus line to 1.0V, in this example.
Lau Benedict
Nguyen Huy
Vu Roxanne
Le Don
McDonnell Boehnen & Hulbert & Berghoff LLP
Rambus Inc.
LandOfFree
Circuit and method for interfacing to a bus channel does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit and method for interfacing to a bus channel, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method for interfacing to a bus channel will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3275125