Static information storage and retrieval – Systems using particular element – Semiconductive
Reexamination Certificate
2002-10-15
2004-05-11
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Semiconductive
C365S159000
Reexamination Certificate
active
06735113
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates generally to integrated circuits, and in particular, to a circuit and a method for performing write operations with thinly capacitively-coupled thyristor (“TCCT”)-based memory cells.
2. Description of Related Art
The rate at which data must be processed is ever increasing in computing-related applications. For example, burgeoning computer graphic applications require faster execution of underlying computational processes to render enhanced three-dimensional images, especially when motion is added. As another example, data network applications demand enhanced computational processes in routing increasing amounts of data (using network elements, such as routers) over decreasing amounts of network bandwidth. The rate at which underlying computational processes are executed depends on the combined functionality of a main processing component, such as a central processing unit (“CPU”) and/or a peripheral device (e.g., graphics processor) and, associated memory. Memory includes both data memory, such as cache (e.g., Static Random Access Memory, or “SRAM”) and main memory (e.g., Synchronous Dynamic Random Access Memory, or “SDRAM”). Data processing rates, however, are generally limited by the manner in which data is exchanged between the processing and memory components, and by the use of conventional memory technology.
Traditionally, the exchange of data between the processing and memory components have been provided by “read” and “write” operations. Access between these components can be either for retrieving data or for programming data into memory cells. These operations, however, can hinder computational processing speeds because processor logic is generally faster than memory access time. That is, processing speed is generally limited by the speed at which data can be stored and retrieved from memory. For example, if a processor initiates a traditional read operation during a pending write operation, then it must postpone retrieving data for processing until the write operation has finished.
To improve memory access time, optimized memory access operations have been developed to coordinate memory access so as to optimize overall processing speed. A conventional approach to performing an optimized memory access is the “read-over-write” operation. In accordance with read-over-write operations, read operations are scheduled to take precedence over write operations, such that initiating a read will interrupt a pending write operation. Consequently, a memory request for stored data is serviced before data is written into memory, thus permitting continued data processing while the write operation is temporarily bypassed. After the read operation is complete, the bypassed write operation can resume.
To overcome the deficiencies of conventional memory technologies, emerging memory technologies have been developed to improve memory access times and operational speed, as well as to minimize power consumption. One such emerging technology relates to negative differential resistance (“NDR”) based devices, and more specifically, to on thinly capacitively coupled thyristor (“TCCT”) memory technology. An example of a TCCT cell, alternatively referred to as a T-RAM cell (i.e., Thyristor-RAM), is disclosed in U.S. Pat. No. 6,229,161 issued to Nemati et al., which is incorporated herein by reference in its entirety.
FIG. 1
shows a pair of representative TCCT-based memory cells
10
as disclosed by Nemati et al., and
FIG. 2
shows a cross-section through one TCCT-based memory cell
10
along the line
2
—
2
.
FIG. 3
shows a schematic circuit diagram corresponding to the example of an embodiment illustrated in
FIGS. 1 and 2
. The TCCT-based memory cell
10
includes an NDR device
12
and a pass transistor
14
. A charge-plate or gate-like device
16
is disposed adjacent to, or as shown, surrounding NDR device
12
. A P+ region
18
of the NDR device
12
is connected to a metallization layer
20
so that a first voltage V
1
, such as an array supply voltage (“V
DDA
”) can be applied to the NDR device
12
through the P+ region
18
. An N+ region of the NDR device
12
forms a storage node
22
that is connected to a source of the pass transistor
14
. Where the pass transistor
14
is a MOSFET, it can be characterized by a channel length, L, and a width, W, where L is the spacing between the source and the drain, and W is the width of the pass transistor
14
in the direction perpendicular to the page of the drawing in FIG.
2
. Assuming a constant applied voltage, a current passed by pass transistor
14
will scale proportionally to a ratio of W/L.
As shown in
FIGS. 1 and 2
, successive TCCT based memory cells
10
are joined by three lines, a bit line
26
, a first word line (WL
1
)
28
, and a second-word line (WL
2
)
30
. The bit line
26
(“BL”) connects a drain
32
of pass transistor
14
to other TCCT-based memory cells
10
. In a similar fashion, pass transistor
14
includes a gate
34
coupled a portion of WL
1
28
. Likewise, gate-like device
16
is coupled to a portion of WL
2
30
.
In performing a read operation in connection with a TCCT-based memory cell
10
, a logic “1” will be read out of the cell if the device is in an “on” state, such that it generates a current representing a logic 1. Similarly, a logic “0” will read out of the cell if the device is an “off” state, such that it produces essentially no current, and hence no voltage. In performing a write operation, a voltage having a relatively high potential, such as V
DD
, is applied to the bit line
26
to write a logical “0” into a targeted TCCT-based memory cell
10
. Conversely, a voltage having a relatively low potential, such as 0 V or ground, is applied to the bit
26
line to write a logical “1” into the TCCT-based memory cell. In both cases, WL
2
is activated to accomplish writing either a logical “0” or “1” into the targeted TCCT-based memory cell
10
.
FIG. 4
is a block diagram of circuit
401
depicting arrays of TCCT-based memory cells and reference memory cells arranged in an open-bit architecture.
FIG. 4
includes a memory array
400
, a reference memory array
414
, a WL
1
/WL
2
decoder
402
, a RWL decoder
412
and a sense amplification circuit
410
. Memory array
400
includes TCCT-based memory cells
404
,
406
, and reference memory array
414
includes TCCT-based reference memory cells
416
,
418
.
As shown, memory array
400
is coupled by bit lines BL
1
, BL
2
, BL
3
, etc., to sense amplification circuit
410
. Also, reference memory array
414
is coupled by reference bit lines RBL
1
, RBL
2
, RBL
3
, etc., to sense amplification circuit
410
. Sense amplification circuit
410
is also connected to complementary input/output lines IO and IO
b
, which are designed to provide data access between an external source (not shown), such as a CPU, and the memory cells
404
,
406
.
In array
400
, each of memory cells
404
,
406
is coupled to a common word line pair (i.e., WL
1
and WL
2
) to form a “row.” For example, memory cells
1
a
,
2
a
, and
3
a
associated with word lines WL
1
a
and WL
2
a
form a first row, and memory cells
1
b
,
2
b
and
3
b
associated with word lines WL
1
b
and WL
2
b
form a second row. Similarly, each of reference memory cells
416
,
418
in array
414
is coupled to a reference word line (i.e., RWL
1
) to form at least one row. Each of the rows in array
400
, and the row in array
414
, are connected to WL
1
/WL
2
decoder
402
and reference RWL decoder
412
, respectively.
WL
1
/WL
2
decoder
402
and reference RWL decoder
412
provide for selection of a row during a memory operation. In particular, WL
1
/WL
2
decoder
402
is connected to word lines WL
1
and WL
2
and decodes at least a portion of a memory address for selecting the appropriate memory cell (or cells, depending on the type of operation, such as block write to a block of memory cells). Similarly, RWL
1
decoder
412
is connected to word line RWL
1
for selecting the appropriate reference memory cell
Jung Seong-Ook
Yoon Sei-Seung
Nguyen Tan T.
T-Ram, Inc.
LandOfFree
Circuit and method for implementing a write operation with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit and method for implementing a write operation with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method for implementing a write operation with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3231174