Circuit and method for high speed sensing

Details Circuit and method for high speed sensing Circuit and method for high speed sensing

2006-08-08

2006-08-08

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S205000, C365S210130, C365S190000, C365S196000, C365S185200, C365S185210

Reexamination Certificate

active

07088630

ABSTRACT:
A circuit and method for sensing a difference between a first signal, such as a signal from the source side of a memory cell, and a second signal, such as a signal from a reference dummy cell, includes developing first and second voltages respectively in response to the first and second signals, determining the time at which the second voltage developed in response to the second signal reaches a threshold level above a latch switching point, and latching a state of the first voltage and second voltage at the determined time using a latch circuit. The threshold level above the latch switching point is set so that potential mismatch in the components of the latch circuit is overcome prior to latching.

REFERENCES:
patent: 5594696 (1997-01-01), Komarek et al.
patent: 5684750 (1997-11-01), Kondoh et al.
patent: 5999454 (1999-12-01), Smith
patent: 6147514 (2000-11-01), Shiratake
patent: 6215339 (2001-04-01), Hedberg
patent: 6292395 (2001-09-01), Lin
patent: 6300816 (2001-10-01), Nguyen
patent: 6396329 (2002-05-01), Zerbe
patent: 6480037 (2002-11-01), Song et al.
patent: 6566914 (2003-05-01), Bruneau et al.
patent: 6798250 (2004-09-01), Wile
patent: 2003/0198112 (2003-10-01), Eleyan et al.
patent: 10-162578 (1998-06-01), None
Tachibana, Suguru, et al., “A 2.6-ns Wave-Pipelined CMOS SRAM with Dual-Sensing-Latch,” 1994 Symposium on VLSI Circuits Digest of Technical Papers IEEE, 1994, 2 pages.
Suh, Jung-Won, et al, “Offset-Trimming Bit-Line Sensing Scheme for Gigabit-Scale DRAM's,” IEEE J. of Solid-State Circuits 31(7), Jul. 1996, 1025-1028.
Van Noije, W.A.M., et al., “Precise Final State Determination of Mismatched CMOS Latches,” IEEE J. of Solid-State Circuits 30(5), May 1995, 607-611.
Kraus, Rainer, “Analysis and Reduction of Sense-Amplifier Offset,” IEEE J. of Solid-State Circuits 24(4), Aug. 1989, 1028-1033.
Huh, Yoonjong, et al., “A Study of Hot-Carrier-Induced Mismatch Drift: A Reliability Issue for VLSI Circuits,” IEEE J. of Solid-State Circuits 33(6), Jun. 1998, 921-927.
Varshney, Ramesh C., et al., “Characterization of an MOS Sense Amplifier,” IEEE J. of Solid-State Circuits SC-13, No. 2, Apr. 1978, 268-271.
Kawahara, Takayuki, et al., “A High-Speed, Small-Area, Threshold-Voltage-Mismatch Compensation Sense Amplifier for Gigabit-Scale DRAM Arrays,” IEEE J. of Solid-State Circuits 28(7), Jul. 1993, 816-823.
Tanzawa, Toru, et al., “Design of a Sense Circuit for Low-Voltage Flash Memories,” IEEE J. of Solid-State Circuits 35(10), Oct. 2000, 1415-1421.
Lovett, Simon J., et al., “Yield and Matching Implications for Static RAM Memory Array Sense-Amplifier Design,” IEEE J. of Solid-State Circuits 35(8), Aug. 2000, 1200-1204.
Sarpeshkar, Rahul, et al., “Mismatch Sensitivity of a Simultaneously Latched CMOS Sense Amplifier,” IEEE J. of Solid-State Circuits 26(10), Oct. 1991, 1413-1422.

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