Circuit and method for generating write data mask signal in...

Details Circuit and method for generating write data mask signal in... Circuit and method for generating write data mask signal in...

2006-12-04

2009-08-18

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S195000, C365S196000

Reexamination Certificate

active

07577057

ABSTRACT:
A circuit for generating a write data mask signal in a synchronous semiconductor memory device includes an output unit and a reset control unit. The output unit controls a write data mask operation of the synchronous semiconductor memory device, latches a write data mask signal, and outputs an internal write data mask signal, in response to an internal clock signal. The reset control unit generates a reset signal for resetting the internal write data mask signal, in response to a write column disable signal indicating an activation end point of a column selection line signal generated when a write operation including the write data mask operation is performed. While the synchronous semiconductor memory device performs a gapless write data mask operation included in a gapless write operation, the reset signal is deactivated so that the write data mask signal is not reset.

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Jan M. Rabaey et al., Digital Integrated Circuit, Prentice Hall, pp. 256-262, 3444-346.

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