Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2007-04-17
2007-04-17
Elms, Richard T. (Department: 2824)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S222000, C365S230080, C365S201000, C326S088000, C327S390000
Reexamination Certificate
active
11141783
ABSTRACT:
A circuit for generating word line control signals that have a stable boosting margin of the sub-word line driver: The circuit includes a first address buffer, a pre-decoder unit, a second address buffer, a main decoder and a circuit for generating a word-line boosting signal. The second address buffer delays a refresh count signal for a predetermined time and generates an enable signal having a predetermined pulse width in response to a row address setup signal and the delayed refresh count signal, and receives and latches a pre-decoded row address signals to output decoded row address signals in response to the enable signal. Accordingly, the circuit for generating word line control signals is capable of obtaining a stable self-boosting margin when the semiconductor memory device operates in a refresh mode.
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English language abstract of the Japanese Publication No. 2-91900.
English language abstract of the Korean Publication No. 2002-0033883.
English language abstract of the Korean Publication No. 2003-0028697.
Elms Richard T.
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
Wendler Eric J.
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