Circuit and method for generating a control signal for a memory

Static information storage and retrieval – Read/write circuit – Signals

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365195, 36523008, 365233, G11C 700

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active

058354220

ABSTRACT:
A memory device (10) for use in an electronic system (12). The system (12) includes a processor (16) that produces a plurality of control signals. The memory device (10) includes a memory array (18) coupled to receive control signals from the processor (18). The memory device (10) also includes a pulse generator (22) that receives at least one of the control signals from the processor (16). The pulse generator (22) includes a latch formed from, for example, a cross coupled pair of NAND-gates (32 and 34). A delayed signal from the latch is coupled to control the reset of the latch such that the latch of the pulse generator (22) outputs a modified control signal for the memory device (10) that has a pulse with a width that is at least as long as the delay.

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patent: 5548560 (1996-08-01), Stephens, Jr. et al.
patent: 5640364 (1997-06-01), Merritt et al.
patent: 5691943 (1997-11-01), Yun

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