Circuit and method for forming a non-volatile memory cell

Details Circuit and method for forming a non-volatile memory cell Circuit and method for forming a non-volatile memory cell

1991-06-28

1993-07-06

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257500, 437 43, H01L 2968, H01L 2978, H01L 2170

Patent

active

052257002

ABSTRACT:
An electrically-erasable, electrically-programmable read-only memory cell (676) is formed at a face of a semiconductor layer (152) having a first conductivity-type and includes a tunnel diode doped region (688) of a second conductivity-type opposite said first conductivity-type formed at the face of semiconductor layer (152). A first highly doped region (688) of the second conductivity-type and a second highly doped region (702) also of the second conductivity-type are formed in the face of semiconductor layer (152) spaced by a sense transistor channel region (696). At least one of the first highly doped region (688) and second highly doped region (702) is spaced from tunnel diode region (688). A thin tunnel insulator (732) is formed on the face of semiconductory layer (152) over tunnel diode doped region (688) and a gate insulator (218) is formed on the face of semiconductor layer (152) over sense transistor channel region (696). A conductive floating gate (708) is provided having respective portions (734, 738) formed on tunnel insulator layer (732) and gate insulator layer (218) and having laterial margins. A conductive control gate (706) is insulatively disposed over floating gate (708) so as to be capacitively coupled thereto. Lateral margins of control gate (706) overlap corresponding laterial margins of floating gate (708) at all points.

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