Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2001-10-04
2004-06-15
Elmore, Reba I. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S158000, C711S167000, C711S203000
Reexamination Certificate
active
06751712
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a memory control circuit and a memory control method for controlling access to memory, and in particular, to access control of virtual channel memory such as virtual channel SDRAM having a plurality of virtual channels.
DESCRIPTION OF THE RELATED ART
The demand for speeding up of synchronous memory is growing more and more these years. A technique effective for the speeding up is virtual channel synchronous DRAM (hereafter referred to as “VCSDRAM”).
The VCSDRAM has several features (input/output circuitry synchronized by an external clock signal, access by use of commands, access by means of burst transfer, etc.) which are common to synchronous DRAM. However, the VCSDRAM is provided with a plurality of high-speed registers called “virtual channels” (hereafter, also referred to as “channels”) in addition to ordinary SDRAM memory cells. Each of the virtual channels can be controlled separately and independently.
In VCSDRAM, read/write operation from outside is conducted directly to each channel as foreground processing, differently from the case of ordinary SDRAM. Meanwhile, intra-memory processes of the VCSDRAM such as data transfer between a memory cell and a channel, precharge of memory cells, refresh, etc. are executed as background processing which is independent of the foreground processing. Therefore, the foreground processing and the background processing can be executed concurrently in VCSDRAM.
In the following, the basic operation of VCSDRAM will be explained referring to Figures.
FIG. 1
is a schematic block diagram for explaining the operation of VCSDRAM.
When data is read out from VCSDRAM
150
(read operation), data readout is executed not from memory cells of the memory cell array
151
but valid data is read out from a channel
152
, differently from the case of ordinary SDRAM (hereafter, the read operation in the VCSDRAM
150
will be referred to as “channel read operation”). In the same way, when data is written into the VCSDRAM
150
(write operation), data writing is not executed directly to memory cells but valid data is written to a channel
152
(hereafter, the write operation in the VCSDRAM
150
will be referred to as “channel write operation”). Hereafter, the operation of the VCSDRAM
150
for copying part of valid data from memory cells to a channel
152
will be referred to as “prefetch operation”. On the other hand, the operation of the VCSDRAM
150
for copying valid data from a channel
152
to memory cells and overwriting old data of the memory cells with the data of the channel
152
will be referred to as “restore operation”.
For the completion of the write operation of the VCSDRAM
150
(that is, for the update of valid data in the memory cells), the restore operation has to be executed after the channel write operation.
Data transfer between a channel
152
and memory cells is generally executed in units of data transfer minimum units which are called “segments”. The size of each segment is generally set to 1/4 of a row address size (the size of each row in the address space).
In the read operation, when valid data exists in a channel
152
(hereafter called “channel hit”), the channel read operation is executed by a memory controller. Such operation will hereafter be called “hit A read”.
When valid data does not exist in a channel
152
(hereafter called “channel miss”) and the row address of the valid data in the memory cells has been in “Active Standby” status, the valid data is first transferred to the channel
152
by the prefetch operation and thereafter the channel read operation is executed. Such operation will hereafter be referred to as “hit B read”.
When the “channel miss” occurred and a row address that is different from a row address where the valid data exists has been in the Active Standby status (hereafter called “row miss”), the status of the row address where the valid data exists is turned to the Active Standby status, the valid data is transferred to the channel
152
by the prefetch operation, and thereafter the channel read operation is executed. Such operation will hereafter be referred to as “miss read”.
In the case of “miss read”, if another background operation (operation which is executed as background processing) is during execution, the execution of the prefetch operation and the channel read operation have to be suspended until the background operation is completed. Therefore, such a wait for the completion of background operation in the case of “miss read” etc. causes the delay of newly occurring access.
In the following, the operation of a conventional memory controller in the case of “channel miss” will be explained referring to
FIGS. 2 and 3
.
FIG. 2
is a timing chart showing the operation of the conventional memory controller when access requests occurred.
FIG. 3
is a schematic block diagram showing an example of the composition of a VCSDRAM module which is controlled by the conventional memory controller.
The timing chart of
FIG. 2
shows a case where three memory access requests are supplied from memory masters
130
. The three memory access requests will be assumed to be read requests, and the three read requests will be referred to as “read request #1”, “read request #2” and “read request #3” in order of occurrence. A memory row address and a segment that occur in the read request #1 will be described as “Row1” and “Seg1”. In the same way, memory row addresses and segments that occur in the read requests #2 and #3 will be described as “Row2”, “Seg2”, “Row3” and “Seg3”, respectively. Further, column addresses that occur in the read requests #1, #2 and #3 will be described as “Col1”, “Col2” and “Col3”, respectively.
It is assumed that the read requests #1 and #2 designate the same memory row address, the same segment and different column addresses. The read request #3 is assumed to designate access to a row address that is different from that of the read requests #1 and #2. Further, it is assumed that each memory cell of the VCSDRAM module is in “IDLE status” (that is, neither bank nor channel is active).
First, for the read request #1, the conventional memory controller (which knows that the current status of the VCSDRAM module is the IDLE status) supplies the memory row address “Row1” to the memory (VCSDRAM module) by use of an ACT (bank active) command, turns a bank A of the memory to the Active Standby status, gives “Seg1” to the memory by use of a PFC (prefetch) command, and thereby transfers valid data to a channel #1. Thereafter, the conventional memory controller supplies the column address “Col1” to the memory by use of a READ (channel read) command and thereby data #1 (da
00
~da
03
) are read out from the channel #1, thereby the memory read operation for the read request #1 is completed.
Subsequently, when the read request #2 is supplied, the conventional memory controller judges that it is “channel hit” since the read requests #1 and #2 designate the same memory row address, the same segment and different column addresses. Therefore, the conventional memory controller issues a READ command to the channel #1, supplies the column address “Col2”, and thereby reads data #2 (db
00
~db
03
) from the channel #1 (that is, executes the aforementioned “hit A read”), thereby the memory read operation for the read request #2 is completed.
Finally, in the case of the read request #3, valid data does not exist in a channel, and a row address that is in the Active Standby status is different from a row address where valid data for the read request #3 exists. Therefore, the case is “row miss”. The conventional memory controller first turns the bank A (which is currently in the Active Standby status) into IDLE status by use of a PRE (precharge) command. Subsequently, the conventional memory controller supplies the memory row address “Row3” to the memory by use of an ACT command, turns a bank B of the memory to the Active Standby status
Elmore Reba I.
McGinn & Gibb PLLC
NEC Corporation
LandOfFree
Circuit and method for executing access control of virtual... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit and method for executing access control of virtual..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method for executing access control of virtual... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3362461