Electrical computers and digital processing systems: support – Data processing protection using cryptography – Tamper resistant
Reexamination Certificate
1998-09-21
2001-03-27
Barron, Jr., Gilberto (Department: 2767)
Electrical computers and digital processing systems: support
Data processing protection using cryptography
Tamper resistant
C713S189000, C380S284000
Reexamination Certificate
active
06209098
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of cryptography. More particularly, the present invention relates to a circuit and method for protecting digital information transferred between integrated circuits of a multi-chip module.
2. Description of Art Related to the Invention
Currently, many companies are now using personal computers and centralized mainframes to store sensitive information (e.g., confidential, proprietary, etc.) in digital form and to perform logical operations utilizing this information. These operations may include, but are not limited to adjusting credit card account balances, bank account balances, metering electronic content usage, applying digital signatures to electronic documents or contracts, etc. Due to the sensitive nature of this information, it has become desirable ensure that its integrity is protected upon being transmitted outside the physical confines of the computer casing as well as during transmission within the casing.
Ideally, digital information may be protected within the computer by encrypting the data before it is transmitted through bus lines that support communications between electronic components each containing an integrated circuit (“IC”) chip. Additionally, to reduce the risk of recovery of digital information stored or processed on-chip, normally accomplished by removing a portion of a single chip package covering the surface of the IC chip and directly examining the IC chip itself, the package may be made of a special packaging material or the integrated circuit may be coated with a special material within the package. These techniques have been in limited use for a number of years in order to protect integrated circuits, targeting the military market, by increasing the difficulty of exposing the integrated circuit through etching, dissolving or grinding away without damaging the surface of the IC chip.
However, for multi-chip packages containing a plurality of IC chips and an interconnect used to transfer information in a non-encrypted format between these IC chips, the special packaging material does not ensure, with a high degree of probability, that a physical attack on the interconnect will be unsuccessful. “Physical attack” is defined as an attempt in recovering sensitive information in a non-encrypted format directly from the internal circuitry of the integrated circuit. The reason that the multi-chip package is particularly susceptible to a physical attack is that access to sensitive data may be achieved directly on the interconnect rather than on the IC chip itself.
In the last few years, the use of multi-chip packages has increased dramatically in order to take advantage of semiconductor fabrication processes improved for different types of circuitry (e.g., memory and logic circuitry). For example, a logic process is typically improved for high performance, high transistor density, and low power with different priorities based on the specific target market. On the other hand, a memory process is typically improved for high memory density, with less emphasis on logic transistor density or performance. However, information transferred between IC chips within a multi-chip package is susceptible to fraudulent modification or illicit observation because the packaging material proximate to the interconnect may be removed without harming any of the IC chips. Thus, systems utilizing a multi-chip module are susceptible to fraud by unauthorized persons unless an additional protective mechanism is implemented.
Therefore, it would be advantageous to develop a multi-chip integrated circuit package (commonly referred to as a “multi-chip module”) that is designed to greatly mitigate the probability of successful physical attack.
SUMMARY OF THE INVENTION
The present invention relates to a circuit and method for protecting digital information transferred between integrated circuit chips. For example, one embodiment features a circuit (apparatus) comprising a first integrated circuit chip and a second integrated circuit chip coupled together through an interconnect. Both the first and second integrated circuit chips include cryptographic engines coupled to the interconnect for encrypting outgoing information being output across the interconnect and decrypting incoming information received from the interconnect.
REFERENCES:
patent: 4092524 (1978-05-01), Moreno
patent: 4271482 (1981-06-01), Giraud
patent: 4310720 (1982-01-01), Check, Jr.
patent: 4467139 (1984-08-01), Mollier
patent: 4471216 (1984-09-01), Herve
patent: 4544833 (1985-10-01), Ugon
patent: 4549075 (1985-10-01), Saada et al.
patent: 4638120 (1987-01-01), Herve
patent: 4656342 (1987-04-01), Ugon
patent: 4656474 (1987-04-01), Mollier et al.
patent: 4907270 (1990-03-01), Hazard
patent: 4907272 (1990-03-01), Hazard et al.
patent: 4910774 (1990-03-01), Barakat
patent: 5068894 (1991-11-01), Hoppe
patent: 5377264 (1994-12-01), Lee et al.
patent: 5396609 (1995-03-01), Schmidt et al.
patent: 5428685 (1995-06-01), Kadooka et al.
patent: 5473692 (1995-12-01), Davis
patent: 5483596 (1996-01-01), Rosenow et al.
patent: 5530753 (1996-06-01), Easter et al.
patent: 5539828 (1996-07-01), Davis
patent: 5559883 (1996-09-01), Williams
patent: 5568552 (1996-10-01), Davis
patent: 5596718 (1997-01-01), Boebert et al.
patent: 5615263 (1997-03-01), Takahashi
patent: 5796840 (1998-08-01), Davis
patent: 5805706 (1998-09-01), Davis
patent: 5805712 (1998-09-01), Davis
patent: 5828753 (1998-10-01), Davis
Barron Jr. Gilberto
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
LandOfFree
Circuit and method for ensuring interconnect security with a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit and method for ensuring interconnect security with a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method for ensuring interconnect security with a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2523835