Circuit and method for enabling semiconductor device burn-in

Details Circuit and method for enabling semiconductor device burn-in Circuit and method for enabling semiconductor device burn-in

2000-01-12

2001-02-06

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S226000

Reexamination Certificate

active

06185139

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to integrated circuits and more particularly to a circuit and method for enabling burn-in operation on integrated circuits with an internally generated voltage supply.
BACKGROUND OF THE INVENTION
Integrated circuit devices are universally prevalent in a wide variety of electronic applications. Integrated circuit manufacturers must guarantee the reliability of integrated circuit devices to meet customer demands. Reliability data is typically acquired by operating the integrated circuit devices for an extended duration to determine the lifetime of the devices. To accelerate this reliability testing process, manufacturers typically employ burn-in procedures to decrease the total time necessary to detect failures. Typically, burn-in has been achieved by simply elevating the operating voltages applied to the device. Increased operating voltages increase the stress to which the devices were subjected and accelerate any failure mechanisms to which the devices were susceptible.
Prior to the advent of deep sub-micron devices, integrated circuits typically operated on a single operating voltage supply (V
dd
). More recently, however, the operating voltage that is applied externally to an integrated circuit device is not the operating voltage that is applied to the internal circuits of the integrated circuit. More specifically, in an increasingly common arrangement, the externally supplied operating voltage is translated to a lower voltage that supplies the internal circuitry of the device. This lower internal operating voltage is necessary in view of the extremely thin oxides characteristic of deep sub-micron devices. To accomplish this translation of operating voltages, such devices typically require a voltage regulator circuit that produces the lower internal operating voltage. Unfortunately, the inclusion of a regulator circuit has an effect on the manner in which burn-in is accomplished. In devices that include a regulator circuit, it is not sufficient to simply raise the externally supplied operating voltage because the regulator circuit will continue to produce a substantially equivalent internal operating voltage. Moreover, it is desirable to achieve an exact burn-in voltage, i.e., the voltage applied to a pin is passed onto the internal circuit. To address this issue, integrated circuit manufacturers have incorporated additional pins into the device to provide a mechanism by which the internal operating voltage can be externally manipulated. It will be readily appreciated, however, that the addition of external pins to the integrated circuit not only increases cost, but is frequently prohibited by industry standard configurations. In other words, integrated circuit manufacturers frequently do not have the freedom to add one or more external pins to a particular device. Therefore, it is highly desirable to implement a solution by which integrated circuit devices that operate on an internal voltage that is less then the externally supplied operating voltage can be subjected to an adequate burn-in test without increasing the device pin count. The solution should be insensitive to process voltage and temperature. Further, it is desirable to enter burn-in operation in a controlled manner.


REFERENCES:
patent: 5349559 (1994-09-01), Park et al.
patent: 5452253 (1995-09-01), Choi
patent: 5497348 (1996-03-01), Tsay
patent: 5557232 (1996-09-01), Shimogawa
patent: 5946242 (1999-08-01), Cho et al.
patent: 6038189 (2000-03-01), Morishita
Chao et al., “A New On-chip Voltage Regulator for High Density CMOS DRAMs,” IEEE, pp. 108-109 (1992).

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