Circuit and method for dynamically controlling the impedance...

Details Circuit and method for dynamically controlling the impedance... Circuit and method for dynamically controlling the impedance...

2002-09-04

2004-08-31

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S086000, C326S083000, C326S063000, C326S081000, C327S108000, C327S112000

Reexamination Certificate

active

06784690

ABSTRACT:

BACKGROUND OF THE INVENTION
FIG. 1
illustrates in block diagram form a microprocessor
10
coupled to memory device
12
via data bus
14
. Although not shown, data bus
14
includes a plurality of conductive lines, each one of which is capable of transmitting a data bit signal between memory device
12
and microprocessor
10
. Microprocessor
10
includes a plurality of input/output (IO) devices (not shown in
FIG. 1
) coupled to respective conductive lines of data bus
14
. IO devices generate the data bit signals which are subsequently transmitted over bus
14
, or IO devices receive data bit signals generated by memory device
12
and transmitted via data bus
14
.
IO devices include drivers for driving a conductive line of a bus in accordance with a data bit signal received by the IO device.
FIG. 2A
is a schematic diagram of a driver
16
which may be employed in one of the IO devices of microprocessor
10
. IO driver
16
shown in
FIG. 2A
should not be considered prior art under 35 USC Section 102 to the invention described or claimed within this specification. In
FIG. 2A
, driver
16
includes a voltage level converter circuit
20
, a pull-up circuit
22
, and a pull-down circuit
24
, all of which are coupled between input and output nodes
26
and
28
. Operational aspects of voltage level converter circuit
20
are described in U.S. application Ser. No. 10/159,684.
Pull-up circuit
22
of
FIG. 2A
includes p-channel field effect transistors (FETs)
30
and
32
while pull-down circuit
24
includes N-channel FETs
40
and
42
. FETs
32
and
42
are coupled to bias voltages V
p
and V
n
, respectively. FETs
32
and
42
limit the gate to source (V
gs
) and gate to drain (V
gd
) of FETS
30
and
32
, respectively, below V
limit
as is more fully described in U.S. application Ser. No. 10/159,684.
Driver
16
receives input data bit signal D
in
16
directly or indirectly from the core of microprocessor
10
. In response to receiving Driver
16
generates output data bit signal D
out
at output node
28
which, in turn, is directly or indirectly coupled to a conductive line of data bus
14
. When driver
16
receives D
in
, voltage level converter
20
generates signal D
mod
as is more fully described in U.S. application Ser. No. 10/159,684. The voltage magnitude of D
mod
varies between V
DD1
, the voltage of a first power supply provided to driver
16
, and an intermediate voltage V
int
depending on the magnitude of D
in
. More particularly, voltage level converter circuit
20
generates D
mod
equal to V
int
when D
in
equals ground (logical 0), and voltage level converter circuit
20
generates D
mod
equal to V
DD1
when D
in
equals V
DD2
(logical 1), the magnitude of a second power supply provided to the core of microprocessor
10
. V
DD1
is greater in magnitude that V
DD2
. V
int
is between V
DD1
and ground in magnitude, and V
int
is at least a threshold voltage V
t
below V
DD1
.
As noted, D
mod
is generated as a function of D
in
. D
mod
is provided to the gate of FET
30
. When D
mod
equals V
int
, FET
30
switches on to create a conductive path between its source and drain. When switched on, current from the first power supply can pass through FET
30
and charge node
28
and the conductive line of bus
14
coupled thereto. Note that FET
32
is switched on and FET
40
is switched off when FET
30
is switched on. When D
mod
equals V
DD1
, FET
30
is switched off and no current can flow therethrough. However, FET
40
is switched on to create a conductive path between its source and drain. When switched on, current from can pass through FET
40
to ground and discharge charge node
28
and the conductive line of bus
14
coupled thereto. Note that FET
42
is switched on when FET
40
is switched. Driver
16
thus generates D
out
by charging or discharging output node
28
as a function of input data signal D
in
.
The signal frequency or rate at which output data bit signals D
out
transmit over data bus
14
can limit the performance of the system shown in FIG.
1
. The higher the transmission frequency, the better. The maximum frequency is a function not only of the time that it takes the electromagnetic wave fronts of data bit signal D
out
to propagate on bus
14
between microprocessor
10
and memory device
12
, but also the time required for data bit signal D
out
to settle to a voltage level that can be reliably recognized by the receiving IO device of memory
12
as being high (logical 1) or low (logical 0).
The time required for D
out
to settle is often referred to as the settling time. There are several factors which affect the settling time. For example, ringing due to reflections from impedance mismatches between the data bus
14
and drivers of IO devices connected thereto is a factor which affects the settling time of the signal.
FIG. 2B
is current/voltage (IV) plot of pull-up circuit
22
of driver
16
at output node
28
. This plot shows the impedance of the pull-up circuit
22
is zero from output voltage equal to zero to output voltage equal to V
1
; the impedance of pull-up circuit
22
varies from output voltage equal to V
1
to output voltage equal to V
2
; the impedance of pull-up circuit
22
varies from output voltage equal to V
2
to output voltage equal to V
DD1
, and; the impedance of pull-up circuit
22
varies for output voltages greater than V
DD1
. If driver
16
could be designed so that the impedance of driver
16
matches the impedance of the conductive line of data bus
14
coupled thereto, driver
16
would not be a source of signal ringing. However, the impedance of pull-up circuit
22
will mismatch the impedance of data bus
14
. As such, the impedance of driver
16
will mismatch the impedance of data bus
14
for certain output voltages.
FIG. 3A
is a schematic diagram of driver
16
with P channel FETS
34
-
36
and N channel FETs
44
-
48
added thereto. IO driver
16
shown in
FIG. 3A
should not be considered prior art under 35 USC Section 102 to the invention described or claimed within this specification. Pull-up circuit
22
of
FIG. 3A
now includes two branches designated normal connected branch
52
and diode connected branch
54
through which output node
28
may be charged when D
in
equals ground. The normal connective branch includes P channel FETs
30
and
32
connected in series between V
DD1
and output node
28
, while the diode connected branch
54
includes P channel FETs
34
-
38
connected in series between V
DD1
and output node
28
. P channel FET
38
is configured as a diode.
The pull-up circuit
22
shown in
FIG. 3A
, unlike the pull-up circuit
22
shown in
FIG. 2A
, has a non-zero impedance at its output for a certain range of output voltages.
FIG. 3B
illustrates IV plots for the normal connected branch
52
and the diode connected branch
54
. The plot for the diode connected branch
54
shows that the impedance of the diode connected branch
54
is constant for output voltages between zero and V
1
; the impedance of the diode connected branch
54
varies between output voltages V
1
and V
2
; and the impedance of the diode connected branch
54
is zero for output voltages greater than V
2
.
FIG. 3B
also illustrates the IV plot for the pull-up circuit
22
in FIG.
3
A. The IV plot for pull-up circuit
22
is the addition of the IV plots for the normal connected branch
52
and the diode connected branch
54
. In
FIG. 3B
, the pull-up circuit IV plot is linear between ground and V
2
. As such, the impedance for pull-up circuit
22
is a non-zero constant between output voltages equal to ground and V
2
. However, due to the influence of the normal connected branch, the IV plot is nonlinear for output voltages which exceed V
2
. In other words, the impedance of the pull-up circuit
22
shown in
FIG. 3B
varies for output voltages which exceed V
2
. As such, the impedance of driver
16
shown in
FIG. 3A
will mismatch the impedance of data bus
14
at least for output voltages that exceed V
2
.
SUMMARY OF THE INVENTION
Disclosed is an input/output

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