Circuit and method for disabling a bitline load

Details Circuit and method for disabling a bitline load Circuit and method for disabling a bitline load

1996-11-01

1998-08-11

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Signals

365190, 365191, G11C 700

Patent

active

057936820

ABSTRACT:
The present invention concerns a circuit and method for disabling the load transistors from the bitlines of a memory array without requiring a fuse. After a particular column is disabled in a redundant memory array system, a short between the particular bitline and ground is detected by a control circuit that shuts off the appropriate bitline load. The disconnecting of the particular bitline load does not affect any of the normal read or write operations of the circuit. The present invention detects whether the short exists and provides the disabling feature while maintaining the ability to distinguish between a normal write condition and a condition that resembles a bitline short. After a write occurs, the bitline load will remain active. The ability of the present invention to distinguish between a normal write and a bitline short allows for transparent operation.

REFERENCES:
patent: 5349560 (1994-09-01), Suh et al.
patent: 5450353 (1995-09-01), Koike
patent: 5577225 (1996-11-01), McClure
patent: 5579265 (1996-11-01), Devin
patent: 5666310 (1997-09-01), Yu et al.

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