Circuit and method for detecting bank conflicts in accessing...

Details Circuit and method for detecting bank conflicts in accessing... Circuit and method for detecting bank conflicts in accessing...

1999-09-27

2002-05-21

Kim, Matthew M. (Department: 2186)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

Reexamination Certificate

active

06393512

ABSTRACT:

BACKGROUND OF THE INVENTION
Main memory 10 (
FIG. 1A
) for a conventional computer is normally implemented by one or more dynamic random access memories (abbreviated as “DRAMs”) that are coupled by a memory bus
11
to an interface circuit
12
(implemented by a “north bridge chip”) that in turn is coupled to a central processing unit (CPU)
13
. Interface circuit
12
is typically coupled to a system bus
14
(such as a PCI bus) that may be coupled to other devices (not shown).
Certain CPUs that require main memory to support a bandwidth of at least 500 Mbytes/s can use a specific type of DRAM called “Direct RDRAM.” A main memory
10
, when implemented with a Direct RDRAM, requires interface circuit
12
to include a specific circuit called “Rambus Access Cell” (abbreviated as RAC)
15
(
FIG. 1A
) that supplies commands as well as row and column addresses to the Direct RDRAM. One example of a conventional Direct RDRAM includes sixteen memory banks
0
-
15
and seventeen sense amplifiers (abbreviated as “sense amps”) S
00
-S
15
(FIG.
1
B). Sense amplifiers S
00
-S
15
temporarily hold the data to be transferred to/from banks
0
-
15
. For example, a sense amp S
01
that is shared between adjacent banks
0
and
1
holds data to/from either of banks
0
and
1
. Due to such sharing of sense amps, two adjacent banks (e.g. bank
0
and bank
1
) cannot be accessed simultaneously in the Direct RDRAM.
This limitation on the simultaneous access of adjacent banks is described in a data sheet entitled “Direct RDRAM™ 64/72-Mbit (256K×16/18×16d),” available from RAMBUS Inc., 2465 Latham Street, Mountain View, Calif., USA 94040 that is incorporated by reference herein in its entirety. In an example wherein the two transactions have the same device and bank addresses, but different row addresses, the data sheet states that “[t]ransaction b may not be started until transaction a has finished. However, transactions to other banks or other devices may be issued during transaction a.” The data sheet further states that the second transaction “must occur a time t
rc
or more after” the first transaction. See the last paragraph in the second column of each of pages 20 and 21.
Conventional use of Direct RDRAMs in computers is described in an article entitled “DIRECT RAMBUS TECHNOLOGY: The New Main Memory Standard,” by Richard Crisp, IEEE Micro, November/December, 1997, pages 18-28 that is also incorporated by reference herein in its entirety. According to the just-described article, such “[d]irect RDRAMs avoid the empty time slots, or ‘bubbles,’ that frequently occur in single clocked SDRAM systems. Bubbles result from inadequate control bandwidth necessary to support page manipulation and scheduling while transferring data to and from random locations. Doubled data rate schemes only aggravate the bubble problem.” Id at page 22.
The article further states that “[u]sers can schedule the data resulting from the row operation to appear immediately after the column operation completes. This highly interleaved condition greatly improves the efficiency of the channel. This interleaving can only happen when the requests target different banks in either the same Direct RDRAM or a different RDRAM on the channel. The more banks in a system, the better the chances are that any two requests are mapped to different banks. The more interleaving that is possible, the more the memory system performance improves. The Direct RDRAM's memory array is divided into banks. . . . all 64-Mbit Direct RDRAMs in development have 16 banks with a page size of 1 Kbyte.” Id at page 23.
The article also states that “[b]ecause a Direct RDRAM spans the entire channel, the CPU accesses each RDRAM independently. So each RDRAM directly adds to the number of memory banks accessible to the memory controller. . . . Since an RDRAM system, as more banks per megabyte than an SDRAM or a DDR system, RDRAM systems boast lower bank conflict rates . . . ” Id.
SUMMARY
A bank conflict detector in accordance with the invention compares at least a portion (e.g. n bank address bits, when there are a total of 2
n
banks in the main memory) of a current address signal (i.e. an address signal generated by a request currently issued to main memory) with a corresponding portion of a to-be-issued memory address signal, to determine if a bank conflict exists. Specifically, in one embodiment, the bank conflict detector includes a number of exclusive OR gates that receive as inputs the two addresses to be compared, and generate an output (also called “XOR result”) that is compared with predetermined patterns to determine if a bank conflict exists. For example, if all banks are independent, then bank conflict detector merely compares the XOR result with 0 (zero) and in case of a match, determines that the two addresses access the same bank.
If one or more of the banks in main memory are dependent (e.g. share sense amplifiers and therefore cannot be simultaneously accessed), then bank conflict detector of this embodiment compares the XOR result (described above) with a pattern formed by a number of consecutive 1s in the least significant bits and a number of consecutive 0s in the most significant bits. If the banks are independent, then the bank conflict detector determines that no bank conflict exists. Otherwise, the bank conflict detector compares at least one of the addresses (both addresses in one implementation) with one or more predetermined patterns (e.g. two patterns in one implementation), and in case of a match determines that a bank conflict does exist, and otherwise determines that no bank conflict exists.
In one implementation, the bank conflict detector checks if the least significant bit is 1 and the remaining bits are zero, and if so determines that a bank conflict does exist. Otherwise, the bank conflict detector repeats the just-described check, except that the predetermined pattern is two least significant bits being 1 and the remaining bits being zero. If the pattern matches, the bank conflict detector checks if two bits of either of the two addresses match the predetermined pattern 2′b01. If so, the bank conflict detector determines that a bank conflict does exist, and otherwise determines that no bank conflict exists. Note that the same pattern 2′b01 is compared with each of the two addresses. In this manner, the bank conflict detector repeats the check with each of a number of predetermined patterns that have sequentially increasing number of 1s, and if any pattern matches, the bank conflict detector also checks the two addresses for predetermined patterns that have an increasing number of 1′s in the least significant bit positions.
In another implementation, the bank conflict detector performs the same actions as those discussed above, except for the predetermined patterns being compared with the two addresses. Specifically, instead of the predetermined pattern 2′b01, another predetermined pattern 2′b10 is used. Similarly, instead of predetermined patterns that have an increasing number of 1s in the least significant bit positions, other predetermined patterns that have an increasing number of 0s in the least significant bit positions are used.
In two other implementations, the bank conflict detector performs the same actions as those discussed above, except that instead of comparing the two addresses with the same predetermined pattern, a single address is compared with two different predetermined patterns. For example, a to-be-issued address (or a currently issued address in another implementation) is compared with each of the two patterns 2′b01 and 2′b10. For each successive increase in the number of bits being used in the comparison of the XOR result, there is a corresponding successive increase in the number of 1 and 0 least significant bits in the two predetermined patterns.


REFERENCES:
patent: 5249280 (1993-09-01), Nash et al.
patent: 5323489 (1994-06-01), Bird
patent: 5432918 (1995-07-01), Stamm
patent: 5440713 (1995-08-01),

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