Circuit and method for decreasing the cell margin during a test

Details Circuit and method for decreasing the cell margin during a test Circuit and method for decreasing the cell margin during a test

1993-09-15

1995-11-21

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

365210, 365190, G11C 2900, G11C 700

Patent

active

054693934

ABSTRACT:
The invention is a monolithic memory device having a circuit and a method for decreasing the cell margin during a test mode. Decreasing the cell margin stresses the memory device during the test mode greater than a stress experienced during normal operation, thus test time can be decreased.

REFERENCES:
patent: 4468759 (1984-08-01), Kung et al.
patent: 5029330 (1991-07-01), Kajigaya
patent: 5276647 (1994-01-01), Matsui et al.
patent: 5339273 (1994-08-01), Taguchi

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