Circuit and method for decoding column addresses in...

Details Circuit and method for decoding column addresses in... Circuit and method for decoding column addresses in...

2007-12-20

2010-02-02

Mai, Son L (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C365S230060

Reexamination Certificate

active

07656729

ABSTRACT:
A column address decoding circuit of a semiconductor memory apparatus includes a predecoder configured to combine a column address and a decoding test signal, thereby outputting a decoding address. A main decoder receives the decoding address, thereby outputting a plurality of column select signals.

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