Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2007-06-05
2007-06-05
Ghebretinsae, Temesghen (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S373000, C327S161000
Reexamination Certificate
active
09891726
ABSTRACT:
Disclosed is a circuit for controlling the duty cycle and jitter of a clock signal. The circuit has an input node for receiving the clock signal and an output node for outputting a processed clock signal having a first edge that is synchronized to an edge of the clock signal and a second edge that is varied so as to provide a predetermined processed clock signal duty cycle. The predetermined duty cycle is preferably a 50—50 duty cycle. The output node may be coupled to baseband circuitry of a wireless communications terminal, such as a cellular telephone. The circuit is constructed to include a plurality of serially connected delay elements that are coupled to the clock signal at the input node. The plurality of delay elements together introduce a nominal one cycle delay into the clock signal. The circuit also includes a phase detector having a first input signal coupled to the clock signal and a second input coupled to an output of the plurality of delay elements for receiving a delayed clock signal therefrom. The phase detector operates so as to generate an error signal that is indicative of a phase difference between the clock signal and the delayed clock signal. The error signal is coupled to at least one of the delay elements for controlling the delay element for minimizing the phase difference between the clock signal and the delayed clock signal. The circuit also includes a first divider circuit having an input coupled to the clock signal, a second divider circuit having an input coupled to an output of a first one of the plurality of delay elements for receiving a one half cycle delayed clock signal therefrom, and a gate having inputs coupled to outputs of the first and second divider circuits and an output coupled to the output node for outputting the processed clock signal.
REFERENCES:
patent: 3629712 (1971-12-01), Clark
patent: 4354188 (1982-10-01), Schneider
patent: 4712224 (1987-12-01), Nelson
patent: 5270643 (1993-12-01), Richardson et al.
patent: 5425017 (1995-06-01), Copley et al.
patent: 5442324 (1995-08-01), Brauns
patent: 5514990 (1996-05-01), Mukaine et al.
patent: 5532632 (1996-07-01), Kent
patent: 5565761 (1996-10-01), Hwang
patent: 5883534 (1999-03-01), Kondoh et al.
patent: 6263192 (2001-07-01), Alderton
patent: 6339833 (2002-01-01), Guo
patent: 6380774 (2002-04-01), Saeki
patent: 6424178 (2002-07-01), Harrison
patent: 6594806 (2003-07-01), Casavant
patent: 6606361 (2003-08-01), Rowell
patent: 6741668 (2004-05-01), Nakamura
patent: 6781419 (2004-08-01), Harrison
patent: 6844895 (2005-01-01), Billerbeck et al.
patent: 6950486 (2005-09-01), Araki
patent: 2002/0085657 (2002-07-01), Boerstler
patent: 2003/0013412 (2003-01-01), Kardach et al.
patent: 0 800 275 (1997-10-01), None
Lee et al., “Low-Noise Fast-Lock Phase-Locked Loop with Adaptive Bandwith Control”, IEEE Journal of Solid-State Circuits, vol. 35, No. 8, Aug. 2000.
“ASMD With Duty Cycle Correction Scheme For High-Speed DRAM”; Jang, S. et al; Electronic Letters; vol. 37, Issue 16; Aug. 2, 2001; pp. 1004-1006.
“The Anti Jitter Circuit for the Suppression of Wideband Phase-Noise”; Underhill, M.J.; IEEE Colloquium on Microwave and Millimeter-Wave Oscillators and Mixers (Ref. No. 1998/480); Dec. 1, 1998; pp. 2/1-2/14.
“Sampling Jitter in High-Speed SI Circuits.pdf”; Jonsson, B.E.; IEEE International Symposium on Circuits and Systems; vol. 1; 1998; pp. 524-526.
“Effect Of Sample Clock Jitter On IF-Sampling IS-95 Receivers.pdf”; Stewart, K.A.; The 8thIEEE International Symposium on Personal, Indoor and Mobile Radio Communications; vol. 2; 1997; pp. 366-370.
“Design Of High-Speed, Low Power Frequency Dividers And Phase-Locked loops in Deep Submicron CMOS”; Razavi, B. et al; IEEE Journal of Solid State Ciruits; vol. 30, No. 2; Feb. 1995; pp. 101-109.
Ghebretinsae Temesghen
Harrington & Smith PC
Nokia Corporation
LandOfFree
Circuit and method for correcting clock duty cycle does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit and method for correcting clock duty cycle, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method for correcting clock duty cycle will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3886462