Circuit and method for controllng the duration of pulses in a co

Details Circuit and method for controllng the duration of pulses in a co Circuit and method for controllng the duration of pulses in a co

1996-03-01

1997-07-01

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Signals

365195, 36523008, 365233, G11C 800

Patent

active

056445385

ABSTRACT:
A memory device (10) for use in an electronic system (12). The system (12) includes a processor (16) that produces a plurality of control signals. The memory device (10) includes a memory array (18) coupled to receive control signals from the processor (18). The memory device (10) also includes a pulse generator (22) that receives at least one of the control signals from the processor (16). The pulse generator (22) includes a latch formed from, for example, a cross coupled pair of NAND-gates (32 and 34). A delayed signal from the latch is coupled to control the reset of the latch such that the latch of the pulse generator (22) outputs a modified control signal for the memory device (10) that has a pulse with a width that is at least as long as the delay.

REFERENCES:
patent: 5493538 (1996-02-01), Bergman
patent: 5519664 (1996-05-01), Collins et al.
patent: 5526320 (1996-06-01), Zagar et al.
patent: 5532961 (1996-07-01), Mori et al.
patent: 5544124 (1996-08-01), Zagar et al.
patent: 5546355 (1996-08-01), Raatz et al.

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