Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2008-06-30
2010-02-23
Cho, James (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S026000
Reexamination Certificate
active
07667483
ABSTRACT:
A calibration circuit that can prevent a calibration operation from being delayed by a dummy capacitor when the calibration circuit starts to operate includes a switch unit configured to connect a calibration node to a precharge node in response to an enable signal. The calibration node is connected to an external resistor. The calibration circuit also includes a code generation unit configured to generate a calibration code in response to a voltage of the calibration node and a reference voltage, a calibration resistor unit configured to drive the calibration node in response to the calibration code and turn-off when the code generation unit is disabled, and a precharge unit configured to precharge the precharge node to a predetermined voltage level when the code generation unit is disabled.
REFERENCES:
patent: 6747475 (2004-06-01), Yuffe et al.
patent: 7288959 (2007-10-01), Lee
patent: 7304495 (2007-12-01), Nygren
patent: 1020030090882 (2003-12-01), None
patent: 1020030096564 (2003-12-01), None
Notice of Allowance issued from Korean Intellectual Property Office on Apr. 30, 2009 with an English Translation.
Cho James
Hynix / Semiconductor Inc.
IP & T Law Firm PLC
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