Circuit and method for controlling memory depth

Details Circuit and method for controlling memory depth Circuit and method for controlling memory depth

1997-02-19

2000-03-21

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

36518901, G06F 1300

Patent

active

060413883

ABSTRACT:
A memory array having a physical depth of 2N-bits (N being an integer) includes control and data bus logic configured to control read and/or write operation in the memory array and to select the depth of the memory array. The control logic may include upper and lower byte control circuitry and the depth of the array may be selected from a group consisting of xN-bits and 2xN-bits, x being an integer. The control and data bus logic may be implemented as metal options within the device to be selected during fabrication to achieve a desired array depth.

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