Circuit and method for controlling inversion of delay locked...

Details Circuit and method for controlling inversion of delay locked... Circuit and method for controlling inversion of delay locked...

2007-05-08

2007-05-08

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233500, C365S230080, C327S147000, C327S149000, C327S156000, C327S175000

Reexamination Certificate

active

11000940

ABSTRACT:
A Delayed Lock Loop (DLL) circuit includes an inversion control circuit. The inversion control circuit includes an inversion decision circuit to determine the inversion of reproduction clock signal by comparing phases of an external clock signal and a reproduction clock signal, and to produce an inversion decision signal including a duty error margin for the reproduction clock signal. The inversion control circuit also includes an output latch to latch the inversion decision signal in synchronization with a start signal to produce an inversion control signal.

REFERENCES:
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patent: 6542609 (2003-04-01), Ryan et al.
patent: 2002/0003747 (2002-01-01), Yahata et al.
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patent: 2003/0219088 (2003-11-01), Kwak
patent: 2004/0041609 (2004-03-01), Lin
patent: 06188740 (1994-07-01), None

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