Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2001-02-27
2004-07-06
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S026000, C326S087000
Reexamination Certificate
active
06759868
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to integrated circuit output drivers. More specifically, the invention relates to both a circuit and a method for adjusting signal transmission parameters of a signal designated for transmission from a first integrated circuit to a second integrated circuit.
2. Discussion of the Related Art
Integrated circuits (ICs) are electrical circuits which incorporate transistors, resistors, capacitors, and other components onto a single semiconductor “chip” in which the components are interconnected to perform a given function. Typical examples of ICs include microprocessors, programmable logic devices (PLDs), electrically erasable programmable memory devices (EEPROMs), random access memory devices (RAMs), operational amplifiers, voltage regulators, and others. Generally, ICs incorporate chip pins, which are configured for enabling electrical interconnection of external electronic components, such as other ICs, high-power amplifiers, discrete external circuit components, and other similar devices. IC electrical interconnection points may be physically and electrically fixed to a printed circuit board via a plurality of solder contact points or pads, which in turn are electrically coupled to a plurality of printed circuit board conductors commonly known as traces. Alternatively, for higher frequency applications using a flip-chip or bump chip, a plurality of solder columns or solder bumps strategically located on the die may be used to provide the physical and electrical interface between the various circuit components on the die and external circuit elements (i.e., other semiconductor dies, ICs, or other such devices). The printed circuit board traces, or IC packages in the case of high-frequency circuit applications, provide a transmission media for input and output signals to and from each IC. In addition, the printed circuit board traces or IC packages may serve to supply any necessary power and electrical ground references to the ICs.
An exemplary configuration is illustrated in FIG.
1
A. In this regard, the figure shows a portion of a printed circuit board
20
having a plurality of contact pads
22
arranged to receive a plurality of ICs
10
a
-
10
d
. Generally, as illustrated in
FIG. 1A
, a plurality of IC pins
12
are electrically and physically associated via the plurality of printed circuit pads
22
. As further illustrated in
FIG. 1A
, a printed circuit board trace
25
may be provided along the upper or lower surface of the printed circuit board
20
or between two or more printed circuit board layers routed to one or both surfaces using a via in order to communicatively couple one or more IC pins
12
from a first IC
10
a
to designated circuits and/or circuit components external to the first IC
10
a
. For example, in
FIG. 1A
, the right most pin
12
associated with IC
10
a
is coupled to the second pin from the left associated with IC
10
b
via the printed circuit board trace
25
.
An IC output driver is typically configured for providing signals designated for transmission to the aforementioned external circuits or circuit components. The IC output driver supplies an amplified version of the signals to be communicated to one or more external devices to a chip pin associated with the IC. It will be appreciated that for high-frequency applications it may be desirable to reduce the number of possible impedance transitions that may confront a particular signal. As previously explained, a semiconductor die may be interconnected to an IC package using a plurality of strategically placed solder columns or solder bumps to physically and electrically connect the various circuits on the die to the IC package. Such an arrangement is illustrated in FIG.
1
B. In this regard,
FIG. 1B
illustrates a cross-sectional view representing the assembly of a flip-chip
10
a
′ to an open cavity ball-grid array
24
. As illustrated, the flip-chip
10
a
′ may contain one or more (one shown for simplicity of illustration) contact pads
22
′ each having its own solder bump
28
. Similarly, the ball-grid array
24
may be configured with one or more spatially separated contact pads
22
′ each having its own solder bump
28
. The flip-chip
10
a
′ may be placed in substantial contact alignment with the open cavity ball-grid array
24
. Heat may then be applied such that the one or both of the solder bumps
28
reaches a melting point. Once the heat is removed and the one or more solder bumps
28
cools, the flip-chip
10
a
′ is both physically and electrically interconnected to the ball-grid array
24
. It will be appreciated that internal conductors within the flip-chip
10
a
′ die, the contact pads
22
′, the solder bumps
28
, along with the associated elements and electrical conductors on the ball-grid array
24
form the transmission media for IC to IC signal transfers. As is known, the ball-grid array
24
may provide a plurality of conductors suitably configured to supply each of the one or more interface signals to pre-designated locations on one or more separate and distinct semiconductor dies.
The block diagram of
FIG. 2
further illustrates an IC to IC signal transfer. As presented in
FIG. 2
, a first IC
10
a
affixed to the printed circuit board
20
may be electrically coupled to a second IC
10
b
as follows. An output driver
14
configured to amplify a signal
30
may supply the amplified signal
30
via a first IC pin
12
a
to a first printed circuit pad
22
a
. The first printed circuit pad
22
a
may be electrically coupled to the printed circuit board trace
25
, which may be further coupled to a second printed circuit pad
22
b
. As illustrated in
FIG. 2
, the second printed circuit pad
22
b
may be coupled to a second IC pin
12
b
associated with the second IC
10
b
. More specifically, the second IC pin
12
b
may be coupled to a designated receiver
16
within the second IC
10
b
. As further illustrated in the block diagram of
FIG. 2
, the IC to IC signal transfer is not point to point limited. In this example, a single output driver
14
to receiver
16
transfer is illustrated. It will be appreciated that a bus
15
may be coupled to the printed circuit board trace
25
, which may further distribute the amplified signal
30
to various devices throughout the printed circuit board
20
. The distribution of the amplified signal
30
from the first IC
10
a
to the second IC
10
b
via the IC pins
12
, the printed circuit pads
22
, and the printed circuit board trace
25
may be modeled using transmission line theory.
The electrical connection described above with regard to the block diagram of
FIG. 2
, contains parasitic resistance, inductance, and capacitance, which interfere with the transmission of the signal
30
from the output driver
14
to the receiver
16
. The parasitic interference increases the load seen by the output driver
14
. Transmission line theory teaches that for transmission lines having a finite length terminated in a non-characteristic impedance, time-varying signals transmitted along the transmission line may suffer from reflected signals. Conversely, for time-varying signals transmitted along transmission lines of a finite length terminated in the characteristic impedance of the transmission line, the reflected signals will vanish.
Impedance mismatches between the output driver
14
and the various signal transmission media of the signal transmission path, as well as, between the receiver
16
and the various signal transmission media of the signal transmission path may produce signal reflections at the output driver end and/or the receiver end of the signal transmission path. These signal reflections may propagate along the transmission path and may potentially result in less than desired system performance. A representative signal
30
including such signal reflections, i.e., reflections
32
and
34
, is depicted in FIG.
3
. Such reflections may cause additional noise and ringing (i.
Helt Christopher G.
Humphrey Guy Marian
Agilent Technologie,s Inc.
Tran Anh Q.
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