Circuit and method for CMOS voltage level translation

Details Circuit and method for CMOS voltage level translation Circuit and method for CMOS voltage level translation

2007-07-03

2007-07-03

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S068000

Reexamination Certificate

active

11090935

ABSTRACT:
A voltage level translation circuit includes a first power supply voltage, a second power supply voltage, wherein the second supply voltage is lower than the first supply voltage, a low voltage input, wherein the low voltage input is referenced from the second supply voltage, a resistive element leaker transistor having a source and a drain, wherein the source is coupled to the first power supply voltage, a PMOSFET having a gate and a source, wherein the source is coupled to the first power supply voltage, and a pulse generator coupled to the gate of the PMOSFET, wherein the pulse generator is capable of controlling the operation of the PMOSFET.

REFERENCES:
patent: 4835419 (1989-05-01), Chappell et al.
patent: 5036226 (1991-07-01), Tonnu et al.
patent: 5160854 (1992-11-01), Martignoni et al.
patent: 5955893 (1999-09-01), Chang et al.

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