Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2008-03-31
2010-06-01
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S032000, C365S185110, C365S189110
Reexamination Certificate
active
07728619
ABSTRACT:
An improved circuit and method for programmable cascading of impedance matching in a multi-chip configuration are disclosed. Handshaking is implemented in cascaded chips by defining a master-slave configuration, and impedance is evaluated in cascaded chips in a non-overlapping manner. The circuit includes a plurality of chips arranged in a cascading configuration. A cascade output pin of a chip is coupled to a cascade input pin of a cascaded chip to enable handshaking between the plurality of chips. The plurality of chips are coupled to a common precision resistor via a common impedance line to enable each chip to calibrate impedance of the chip. Each of the plurality of chips includes a control circuit. Each control circuit includes a state machine circuit. The control circuit is configured to control a non-overlapping clock cycle of each chip during which the impedance of the chip is evaluated.
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Parameswaran Suresh
Tran Thinh Dinh
Tzou Joseph Jengtao
Cypress Semiconductor Corporation
Tan Vibol
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