Circuit and method for calculating a logical combination of...

Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor

Reexamination Certificate

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Details

C326S093000, C326S098000, C326S114000, C326S115000, C326S121000

Reexamination Certificate

active

11463190

ABSTRACT:
A circuit for calculating a logical combination of two input operands includes a first input for receiving a first dual rail signal having data values of the first input in a calculation cycle and precharge values in a precharge cycle, a second input for receiving a second dual rail signal having data values of the second input in the calculation cycle and precharge values in the precharge cycle, and an output for outputting a third dual rail signal having result values in the calculation cycle and precharge values in the precharge cycle. Furthermore, the circuit has a logic circuit for determining the result values according to the logical combination from the data values of the first input and the second input and for outputting the result values in the calculation cycle at the output, and a precharge circuit designed to impress precharge values in the output already when precharge values are detected at a single input, or designed to terminate impressing the precharge values only when the first dual rail signal and the second dual rail signal have data values.

REFERENCES:
patent: 6043674 (2000-03-01), Sobelman
patent: 6066965 (2000-05-01), Blomgren et al.
patent: 6509761 (2003-01-01), Taki
patent: 6717438 (2004-04-01), Choe
patent: 2002/0101262 (2002-08-01), Taki
patent: 103 44 647 (2005-02-01), None
Stefan Mangard, et al., “Side-Channel Leakage of Masked CMOS Gates,” Institute for Applied Information Processing and Communications, Graz, Austria, Feb. 18, 2005.
Thomas Popp, et al., “Masked Dual-Rail Pre-Charge Logic: DPA-Resistant Circuits without Routing Constraints,” Institute for Applied Information Processing and Communications, Graz, Austria, Feb. 11, 2005.

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