Static information storage and retrieval – Systems using particular element – Capacitors
Reexamination Certificate
2000-01-11
2001-03-27
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Capacitors
C365S226000
Reexamination Certificate
active
06208552
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to the field of memory devices, and more particularly to a circuit and method for biasing the charging capacitor of a semiconductor memory array.
BACKGROUND OF THE INVENTION
The peripheral circuitry of a semiconductor memory array often includes a charging capacitor coupled between a reference voltage and ground. The stored charge of the charging capacitor is passed through the word line decoding circuits and word line detection circuits to charge the reference capacitors of the memory cells of the word line or word lines selected by the decoding and detection circuits. Because the charging capacitor must provide a reference voltage to each word line in the memory array, the charging capacitor often has a large surface area and is prone to failure upon the application of a sufficiently high voltage differential across the plates of the charging capacitor. The charging capacitor may also be coupled to ground from an oxide layer common to other components of the semiconductor memory array, including the gates of transistors in the memory. As a result, failure in these other components also connected between the common oxide layer and ground will result in failure of the charging capacitor as well.
Conventionally, the charging capacitor is biased during operation and testing by placing a reference voltage at the anode of the capacitor and grounding the cathode of the capacitor. During the testing of DRAM semiconductor memories, the voltage level applied to the word lines of the memory array is raised for an extended period. During burn-in testing, for example, the voltage applied to each word line is elevated from a normal level to a higher voltage for an extended period, possibly 20 hours or longer. Other testing modes are possible, including operating-life testing. As compared to the voltage applied during burn-in testing, the voltage applied to the word lines during operating-life testing is lower but is applied for a longer period, possibly 1000 hours or longer. Burn-in testing and operation-life testing are necessary to insure an adequate length of operating life for the semiconductor memory device. Each of these testing modes employs accelerated operating conditions over shorter period to simulate the effects of normal operating conditions over a longer period.
Because the charging capacitor may share the same oxide layer as the gates of the memory array, the elevated voltages applied to the word lines of the memory array during testing are also applied to the anode of the charging capacitor during the entire testing sequence. Thus, imperfections in the oxide layer shared between the transfer gates and the charging capacitor are often manifested in a failure of the charging capacitor. Unlike each word line of the semiconductor memory array, however, the charging capacitor is stressed during the entire testing sequence as the entire elevated testing voltage is applied at the anode of the charging capacitor, often resulting in excessive failure rates of the charging capacitor due to inadequate testing parameters.
SUMMARY OF THE INVENTION
In accordance with the present invention, a circuit and method for biasing the charging capacitor of a semiconductor memory array is provided that substantially reduces or eliminates the problems and disadvantages of prior methods of biasing charging capacitors of semiconductor memory arrays.
The cathode of the charging capacitor of the present invention is coupled to a switch that is able to switch the cathode to one of several voltage levels depending on the testing or use condition of the semiconductor memory array. The voltage levels that may be connected to the cathode are derived independently of the reference voltages applied at the anode of the charging capacitor. The switch switches between the voltage levels at the cathode to avoid overstressing the charging capacitor during testing of the semiconductor memory array. The switchable voltage levels at the cathode are graduated to insure that the differences in acceleration factor between successive testing or use conditions are sufficiently great to test the integrity of the charging capacitor itself.
A technical advantage of the present invention is a provision of a circuit and method for biasing a charging capacitor in which the differential voltage applied to the charging capacitor is adjustable depending on the testing or use condition of the semiconductor memory array.
Another technical advantage of the present invention is the provision of a circuit and method for preventing a charging capacitor from becoming overstressed during testing of the semiconductor memory array.
Still another technical advantage of the present invention is the provision of a circuit and method for biasing a charging capacitor that insures an adequate difference in acceleration factors between the successive testing or use conditions to insure the adequate testing of the charging capacitor itself.
REFERENCES:
patent: Re. 32236 (1986-08-01), Scheuerlein
patent: 3387286 (1968-06-01), Dennard
patent: 4044340 (1977-08-01), Itoh
Brady, III. Wade James
Fears Terrell W.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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