Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-09-25
2004-08-31
Fabmyl, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06784496
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to integrated circuits, and more particularly to a circuit and method for an integrated charged device model clamp.
BACKGROUND
Integrated circuit (“IC”) technology continues to improve, resulting in ICs with increasing density and devices with smaller and smaller geometries. As the devices become more miniaturized, however, they generally become more susceptible to electrostatic discharge (“ESD”) damage. If ESD is not properly contained, it can lower a device's reliability or even destroy the device.
An ESD event typically occurs when an IC (e.g., a metal oxide semiconductor (“MOS”) IC) is handled by a human being or by a machine. During an ESD event, a large voltage is applied to the IC. Generally, to avoid damage to the IC during an ESD event, ESD protection devices are typically fabricated on the IC and connected to the IC input/output pads and input/output circuits and other internal nodes of the IC. As used herein with respect to a component in an IC, the phrase “input/output” means that the component is used for either input or output, or both. ESD protection devices generally provide discharge paths so that the internal circuits of the IC are not damaged during the ESD event.
Different ESD tests may be used to evaluate the effectiveness of ESD protection devices. Three ESD tests typically used include: the human body model (“HBM”) test, a machine model (“MM”) test and a charged device model (“CDM”) test. Different ESD protection devices may be needed to optimize the level of ESD protection provided for the different ESD tests.
A detailed description of CDM events and IC design guidelines is provided in Timothy Maloney, “Designing MOS Inputs and Outputs to Avoid Oxide Failure in the Charged Device Model,” EOS/ESD SYMPOSIUM PROCEEDINGS, 1988, pp. 220-27. Generally, a CDM test simulates a charged device contacting a grounded surface (e.g., metal), typically associated with automated handling equipment in the production/manufacturing environment. A CDM test may be performed in the following manner. First, the device to be tested is charged. Most of this charge is stored in the VDD voltage supply rail and/or the ground supply rail within the device. Then one of the pads of the charged device is connected to an external ground. The charges stored in the VDD and/or ground supply rail then find pathways flowing to the pad under test, typically dissipating the charge within nanoseconds, thus testing the ESD protection devices implemented in the IC.
While primary ESD structures (e.g., PDNMOS, BTNMOS, dual-diodes) placed near the input/output pads of a device generally provide protection against HBM and MM events, they do not necessarily provide sufficient protection against CDM events. Generally, the most common damage caused by a CDM event is the rupture of thin dielectrics in the IC, such as MOS gate dielectrics or capacitor dielectrics. CDM clamps, are therefore used to provide protection of internal IC input circuits against charged device ESD events. Generally, in prior art circuits, the CDM clamp devices are separated from the internal input circuit transistors, with a metal interconnect system providing the connections between the CDM clamps and the input circuit.
A disadvantage of the prior art circuits is that the metal/contact/via physical characteristics of this metal interconnect system may significantly increase the parasitic resistance and inductance of the circuit. Generally, in order for CDM clamps to be effective, the parasitic resistance and inductance between the ground/power-supply connections of the internal input circuit and the ground/power-supply connections of the CDM clamps must be minimized. Because the input circuitry may not reside in close physical proximity to its CDM ESD protection structure, however, there may be significant parasitic resistance and inductance in the metal ground bus between the CDM ESD structure and the input circuit inverter/buffer.
Generally, the parasitic inductance and resistance between the ground connection of the CDM clamp and the ground connection of the input circuit act in series with the clamp voltage of the CDM clamp, building up excess voltage across the pin being protected and ground. Likewise, the parasitic inductance and resistance between the power-supply connection of the CDM clamp and the power-supply connection of the input circuit act in series with the clamp voltage of the CDM clamp, building up excess voltage. Because a CDM event may have a peak current level of about 5-10 amps, with a rise time of a few hundred picoseconds, the voltage drop along the ground/power-supply bus metallization may be significant with respect to the CDM clamp voltage. The total voltage drop may be high enough to degrade or rupture the gate oxides of the input transistors.
SUMMARY OF THE INVENTION
These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention in which a CDM clamp circuit is integrated into the interface circuit being protected on the IC. Generally, the integrated CDM clamp circuit and interface circuit are adjacent to each other and share a common device element or component, thus eliminating the need for a metal interconnect. Because there is no interconnect, the parasitic resistance and inductance are also minimized or eliminated from the circuit, thus reducing or eliminating the excessive voltage drop present in prior art circuits.
Preferably, the CDM clamp circuit is integrated into the circuit that it is protecting by having the two circuits share the same silicon source region. In a preferred embodiment input circuit, the same diffusion region is the source of both the input transistor and its associated CDM clamp transistor. In one preferred embodiment, a PMOS input transistor and a PMOS CDM clamp transistor share a single p+ diffusion region. In another preferred embodiment, an NMOS input transistor and a NMOS CDM clamp transistor share a single n+ diffusion region.
An advantage of a preferred embodiment of the present invention is that it generally eliminates the need for a metal interconnect between the sources of the CDM clamp device and the internal circuit device.
Another advantage of a preferred embodiment of the present invention is that, by eliminating the source metal interconnect, it generally minimizes or eliminates parasitic resistance and inductance between the ground/power-supply connection of the internal input circuitry and the ground/power-supply connection of the CDM clamp device.
Another advantage of a preferred embodiment of the present invention is that it reduces the area on the IC needed for CDM protection because the devices are located directly adjacent to each other and because each CDM clamp shares a source region with the transistor that it is protecting.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
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pat
Brodsky Jonathan
Steinhoff Robert
Vrotsos Thomas A.
Brady III W. James
Fabmyl Wael
Farahani Dana
Moore J. Dennis
Telecky , Jr. Frederick J.
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