Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-07-01
1999-11-23
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711207, G06F 1212
Patent
active
059918543
ABSTRACT:
A circuit used to control the modification of content within memory implemented within an address translation unit. This memory includes a plurality of entries which contain virtual and physical addresses associated with an address translation. The circuit includes an update control circuit coupled to the address translation circuit. The update circuit is configured to set an entry to an invalid state or point to an entry to be loaded with a new address translation. The circuit further includes a flush control circuit that is configured to control the update control circuit. Such control includes setting an entry to an invalid state upon detecting a particular event.
REFERENCES:
patent: 4218743 (1980-08-01), Hoffman et al.
patent: 4381540 (1983-04-01), Lewis et al.
patent: 4933937 (1990-06-01), Konishi
patent: 5155825 (1992-10-01), Moughanni et al.
patent: 5293488 (1994-03-01), Riley et al.
patent: 5390173 (1995-02-01), Spinney et al.
patent: 5428615 (1995-06-01), Backes et al.
patent: 5509131 (1996-04-01), Smith et al.
patent: 5592625 (1997-01-01), Sandberg
patent: 5764944 (1998-06-01), Hwang et al.
Chan Eddie P.
Portka Gary J.
Sun Microsystems Inc.
LandOfFree
Circuit and method for address translation, using update and flu does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit and method for address translation, using update and flu, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method for address translation, using update and flu will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1235197