Pulse or digital communications – Receivers – Interference or noise reduction
Reexamination Certificate
1997-08-29
2001-02-20
Vo, Don N. (Department: 2734)
Pulse or digital communications
Receivers
Interference or noise reduction
C375S278000, C375S284000
Reexamination Certificate
active
06192090
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit and method for calculating a decision error of a digital signal in a digital modulation system and, more particularly, to a circuit and method for adaptively calculating a decision error by limiting a phase detecting decision region.
2. Description of the Related Art
Recently, there has been a demand for a color television having a large-sized screen with high resolution and high picture quality along with realistic sound. In line with this recent trend, the first HDTV (High Definition TV) broadcasting has been implemented on the basis of an analog transmission system. The HDTV transmission system developed in Japan is called a MUSE (Multiple Sub-Nyquist Sampling Encoding) transmission system. The United States has used a VSB (vestigial sideband) modulation adopted by the GA (Grand Alliance) committee as a modulation system of the HDTV system, and proposed schematic configurations therefor. The VSB modulation is used as a method of modulating an analog video signal in existing TV broadcasting.
The GA-HDTV proposed by the GA committee transmits a digital modulation signal by using a VSB signal. In an initial DSC (Digital Spectrum Compatible) HDTV, 2-level and 4-level VSB modulation systems using 2 and 4 levels have been adopted. However, in the GA-HDTV, an 8-level VSB modulation system using 8 levels and a 16-level. VSB modulation system applied to a high speed cable mode have been adopted. To demodulate the VSB signal, the GA committee has proposed a VSB receiver of the HDTV having the following features.
The VSB receiver of the HDTV proposed by the GA committee implements sampling by a unit of symbol rate by detecting data by only a signal of an I (In-phase) channel unlike other demodulators of the digital modulation signal. Therefore, the VSB receiver of the HDTV proposed by the GA committee has a very simple structure compared with a receiver of QAM (Quadrature Amplitude Modulation) etc. using both an I channel and a Q (quadrature) channel. Moreover, since received data is processed by a unit of symbol rate, it is possible to detect the data even though a processing speed is relatively lower than a fractional rate receiver.
The proposed VSB receiver uses synchronous detection for recovering a carrier wave when detecting digital data from the VSB modulation signal. The synchronous detection has an advantage in that it is possible to detect the data with a lower error rate than asynchronous detection at the same signal-to-noise ratio. However, the structure of the VSB receiver is complicated due to a carrier wave recovery circuit. Therefore, the proposed VSB receiver uses a FPLL (Frequency and Phase Locked Loop) and a PTL (Phase Tracking Loop) circuit in detecting the phase of a transmission signal for the synchronous detection.
The FPLL performs phase tracking of the transmission signal by using a pilot signal contained in the VSB signal. This FPLL can be easily achieved by a frequency error detecting circuit of a conventional PLL (Phase Locked Loop) and is described in GA-HDTV system recommendations. An output of the FPLL passes though a channel equalizer and is further applied to an input of the PTL circuit. The PTL circuit eliminates phase noise, that is, phase error which is not eliminated in the FPLL. The structure of the PTL circuit of the GA-HDTV receiver is not greatly different from that of a DDCR (Decision Directed Carrier Recovery) circuit. However, the PTL circuit estimates rotation components of signal points by using sampling data of an input I channel and compensates a phase error value. In data of the I channel, information to be actually transmitted is contained. The Q channel has no function for transmitting actual information but reduces a spectrum of the modulation signal. If there is a phase error during demodulation, not only data of the I channel but also data of the Q channel is contained in the sampling data of the I channel. Therefore, in order that the PTL circuit corrects the phase error, information of the Q channel is also needed. The information of the Q channel can be easily obtained by filtering the data of the I channel by use of a Hilbert transform filter.
FIG. 1
is a block diagram showing a GA-HDTV receiver proposed as a standard by the GA committee. The overall operation for the VSB receiver of
FIG. 1
is described in a paper entitled “DESIGN AND PERFORMANCE ANALYSIS OF PHASE TRACKER FOR SYNCHRONOUS VSB RECEIVER” published in the Autumn Synthesis Science Publication Paper Collection issued in 1994 by the Korean Institute of communication science.
As shown in
FIG. 1
, a system using the digital VSB modulation decides a digital signal through an equalizer
50
and a PTL
60
and utilizes a decision error value. For digital signal decision through the equalizer
50
and the PTL
60
, the digital signal is decided to the nearest symbol by using a received I signal as shown in FIG.
2
. To reduce the chance of a wrong decision due to the phase error etc., there is used an adaptive decision method calculating a slope indicated by an oblique line in
FIG. 2
by using a Q signal obtained from the I signal. While a fixed decision region is liable to result in an incorrect decision even from a small vestigial phase error, an adaptive decision region can reduce a decision error by obtaining the slope from data of a constant number. However, a circuit for deciding the digital signal to both I and Q axes becomes complicated.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a circuit and method for calculating a decision error according to the state of an input signal by adaptively limiting a decision region in a digital modulation system.
It is another object of the present invention to provide a circuit and method for simplifying hardware construction and performing a stable operation.
The present invention includes a circuit for adaptively calculating a decision error of a digital signal by limiting a decision error region in a digital modulation system. One embodiment of the circuit includes a digital filter for Hilbert transform filtering I channel data to generate Q channel data which differs in phase from the I channel data, a delayer for delaying the I channel data for a filtering time of the digital filter, a reference signal interval processor for receiving the I channel data and generating a reference signal pulse for detecting a slope, an estimation and adaptive decision error detector for receiving the I channel data delayed by the delayer during a detected interval of the reference signal pulse, deciding symbol data and generating an adaptive decision error signal according to a detected slope, and a slope detector for receiving the decision error signal generated from the estimation and adaptive decision error detector and the Q channel data generated from the digital filter, detecting the slope during the detected interval of the reference signal pulse and generating the accumulated slope.
The present invention also includes a method for adaptively calculating a decision error of a digital signal by limiting a decision error region in a digital modulation system. In one embodiment, the method includes the steps of detecting a reference signal pulse from I channel data, receiving the I channel data and Q channel data during a detected interval of the reference signal pulse and deciding symbol data by the I channel data and Q channel data of a limited region, and adaptively calculating a decision error value according to a calculated slope.
The present invention will be more specifically described with reference to the attached drawings.
REFERENCES:
patent: 4447910 (1984-05-01), Smith et al.
patent: 5406587 (1995-04-01), Horwitz et al.
patent: 5602601 (1997-02-01), Kim et al.
patent: 5796786 (1998-08-01), Lee
Phu Phuong
Samsung Electronics Co,. Ltd.
Sughrue Mion Zinn Macpeak & Seas, PLLC
Vo Don N.
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