Circuit and method for a memory device with p-channel isolation

Details Circuit and method for a memory device with p-channel isolation Circuit and method for a memory device with p-channel isolation

1999-07-26

2000-06-27

Phan, Trong

Static information storage and retrieval

Read/write circuit

For complementary information

365207, G11C 700

Patent

active

060814616

ABSTRACT:
A circuit and method for limiting voltage swing on the complementary bit lines of a memory device. Complementary bit lines of the memory device are coupled to a sense amplifier through first and second p-channel isolation devices. A low voltage is applied to a gate of the p-channel isolation devices to activate the p-channel isolation devices such that one of the first and second p-channel isolation devices establishes the low logic level on one of the complementary bit lines at a voltage that limits the swing on the complementary bit lines.

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