Circuit and method for a memory device with P-channel isolation

Details Circuit and method for a memory device with P-channel isolation Circuit and method for a memory device with P-channel isolation

1997-08-14

1999-02-23

Nelms, David

Static information storage and retrieval

Read/write circuit

Differential sensing

365208, 365190, 365226, G11C 702, G11C 700

Patent

active

058751416

ABSTRACT:
A circuit and method for limiting voltage swing on the complementary bit lines of a memory device. Complementary bit lines of the memory device are coupled to a sense amplifier through first and second p-channel isolation devices. A low voltage is applied to a gate of the p-channel isolation devices to activate the p-channel isolation devices such that one of the first and second p-channel isolation devices establishes the low logic level on one of the complementary bit lines at a voltage that limits the swing on the complementary bit lines.

REFERENCES:
patent: 4807195 (1989-02-01), Busch et al.
patent: 4897568 (1990-01-01), Chern et al.
patent: 4991142 (1991-02-01), Wang
patent: 5029136 (1991-07-01), Tran et al.
patent: 5315555 (1994-05-01), Choi
patent: 5636170 (1997-06-01), Seyyedy
patent: 5680364 (1997-10-01), Lee
patent: 5689461 (1997-11-01), Kaneko et al.

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