Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
1998-08-26
2001-01-30
Beausoliel, Jr., Robert W. (Department: 2785)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C713S500000, C713S501000, C713S400000, C713S401000, C714S700000, C327S149000, C327S152000, C375S371000
Reexamination Certificate
active
06182236
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an electronic system and, more particularly, to the distribution of a clock signal among multiple subsystems of the electronic system with minimal differential (i.e., “skew”) among times in which the clock transitions arrive at select subsystems.
2. Description of the Related Art
An electronic system, such as a computer or microprocessor encompasses numerous subsystems necessary to carry out its intended function. A subsystem which utilizes a clock signal is defined as any component (active or passive) which triggers from the clock signal, or may include multiple components coupled together in sequential fashion. Interconnected transistor and resistor components include, for example, a flip-flop, latch, register, etc. A subsystem may be sufficiently large and contain multiple sequential elements coupled together to carry out a systematic result.
Regardless of the relative size of a subsystem, it is important that a sequential subsystem be clocked or modulated by a clocking signal. Thus, the subsystem requires a clocking signal input to the subsystem to control reception and transfer of data also arriving upon the subsystem.
Proper operation of an electronic system requires that system be synchronized with the clocking signal. Thus, the clocking signal should arrive at select subsystems at the same time. Otherwise, reliable data reception and transmission is not ensured. For example, if data is clocked into one subsystem later than data is clocked into another, the earlier-clocked data may contend with and destroy the later-clocked data before that data is properly stored. The problem of data contention and the lack of concurrency by which the clocking signal arrives at each of the synchronized subsystems is often referred to as “clock skew”. Increases in clock skew correspondingly increases the amount of time that the data must remain stable on the bus and/or conductor. This, in turn, will increase the time required for each data transfer on the bus and therefore will reduce the speed of the bus. A conventional solution to clock skew involves accounting for differences in arrival time by buffering distally located subsystems. This requires knowing where the subsystems are located relative to one another—either their location within a monolithic silicon substrate or within a printed circuit board (PCB) between monolithic silicon. Knowing which subsystem is to receive a buffered clocking signal also assumes that the designer can forecast an accurate propagation delay from the clocking source to each destination fed by the clocking signal. Knowing the relative location and propagation delay is difficult to accurately model especially since clock skew will vary depending on fabrication processes and operating temperatures.
It would be desirable to seek an electronic system employing a clock generation circuit which can account (i.e., compensate) for varying clock skews while the electronic system is operating. Operating conditions of the electronic system ensures an accurate indication of the actual clock skew. Knowing the actual clock skew and offsetting that clock skew immediately at the clock signal destination would prove advantageous. It would be further beneficial for the improved clock generation circuit to be used at multiple subsystems to account for the dissimilar clock skews among those subsystems. The clock skews can arise from dissimilar resistive and capacitive loads seen across multiple subsystem destinations of a single conductor carrying the clocking signal. Accordingly, the desired electronic system can make the clocking transitions occur more quickly in greater skew subsystems and yet make the clocking transitions occur less quickly in lesser skew subsystems, each of which are coupled to a single conductor containing the clocking signal.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by an improved electronic system, clock generation circuit and method hereof. The present electronic system incorporates a clock generation system prior to and within one or more subsystems which receive a single clocking signal. The clock generation signal either advances or delays the clocking signal depending on the amount of load associated with the particular subsystem to which it is connected. As such, a clocking signal forwarded to multiple subsystems can be adjusted (i.e., phase-skewed) by the clock generation circuit prior to it being received upon the respective subsystem. Adjusting the clocking signal arriving upon a plurality of subsystems ensures data is received, processed, and transferred synchronously among those subsystems. Accordingly, the duration at which the data must remain stable can be significantly reduced, thereby increasing the overall speed of the electronic system.
At least one subsystem associated with the electronic system may include a clock generation circuit to offset or compensate for skew induced upon the clocking signal by the subsystem. It is known that different subsystems have different loads and therefore attribute different skews to clocking signals fed to those subsystems. The present clock generation circuit offsets differences in skews to insure the phase and/or transitions of a clocking signal arrives at each subsystem at relatively the same time.
According to one embodiment, the clock generation circuit includes a clocking signal adapted to clock a load associated with a subsystem to which the clock generation circuit is attributed. A first reference clock is provided to the clock generation circuit and comprises a plurality of phases. A first phase of the first reference clock can be chosen as a second reference clock. A selection unit is coupled to receive the clocking signal and the second reference clock to select a second phase of the first reference clock. The second phase is used to drive the clocking signal based on the timed relationship between the second reference clock and the clocking signal.
According to yet another embodiment, the first reference clock is fed into a phase detector of a first phase-locked loop (“PLL”), along with the output of a voltage controlled oscillator also associated with the first PLL. The voltage controlled oscillator may include a series-connected chain of inverters. Taps from select outputs of those inverters are designed to carry multiple phases of the first reference clock, one of which is chosen as the second reference clock.
According to yet another embodiment, the clock generation circuit includes a second PLL. Similar to the first PLL, the second PLL employs feedback and a phase comparison between a feedback signal and a reference signal. While the first PLL compares the voltage controlled oscillator output to the first reference clock, the second PLL compares the clocking signal to the second reference clock. If the clocking signal is phase shifted (or skewed) relative to transitions of the second reference clock, then the second PLL will select another phase (or another tap) derived from the inverter chain. This will cause an earlier or later phase of the first reference clock to be driven upon the clocking signal. Eventually, the proper tap will be selected to ensure the clocking signal is phase synchronized with the second reference clock similar to phase synchronization between the voltage controlled oscillator output and the first reference clock.
Employing a cascaded arrangement of two PLLs allows accurate measurement of skew attributed to the clocking signal. The clocking signal and, more importantly, the skew upon that clocking signal is fed back to the input of the second PLL where it is compared with the second reference clock. For example, if the clocking signal resulting from a large load condition lags the second reference clock, then the second PLL operates as a selection unit by selecting an earlier tap or phase of the first reference clock generated from the first PLL. The second PLL not only selects an earlier phase, but drives that phase upon the clocking signa
Culley Paul R.
Le Hung Q.
Beausoliel, Jr. Robert W.
Compaq Computer Corporation
Conley Rose & Tayon
Crockett Robert G.
Daffer Kevin L.
LandOfFree
Circuit and method employing feedback for driving a clocking... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit and method employing feedback for driving a clocking..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method employing feedback for driving a clocking... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2452448