Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-11-16
2003-04-29
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06557148
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a circuit analysis tool for use in developing an LSI (large scale integrated circuit).
A circuit simulator, a logical simulator and the like are known as circuit analysis tools to be used during the design phase of a semiconductor integrated circuit. The circuit simulator measures the voltages and currents of internal circuit elements for the solution of the circuit equation specified on the basis of circuit connection information described at the transistor level. As the circuit simulator, SPICE2 developed by University of California, Berkeley (UCB) is popularized.
On the other hand, the logical simulator examines the signal levels of “1” and “0” at nodes inside the circuit on the basis of the circuit connection information described at the logical level.
In accordance with an increase in scale of the semiconductor integrated circuit to be designed, an increasing time required for the simulation has become a problem. It can be considered to reduce the processing time as a solution to the above problem by means of a simple simulation device such as a timing simulator instead of a circuit simulator of the aforementioned SPICE2 or the like. However, the simple simulation device such as the above-mentioned timing simulator has low accuracy and sometimes fails in obtaining a satisfactory result.
As another method for reducing the time required for the simulation, it can be considered that the designer himself or herself manually specifies the circuit to be subjected to processing among all the circuits. However, the work of manually extracting a specific circuit element from a large scale semiconductor integrated circuit is a very complicated work and not practicable.
In order to reduce the time necessary for the simulation, there is proposed a simulation device that omits overlapped calculating operations, for example, by excluding a circuit element that has not been changed from the time of execution of the preceding simulation after circuit correction from the objects to be processed, consequently reducing the time required for the second and subsequent simulating operations (Japanese Patent Laid-Open Publication No. HEI 5-312905). However, according to the aforementioned simulation device, the time required for the first simulation cannot be reduced since the first simulation necessarily includes all the circuits as the objects to be processed.
SUMMARY OF THE INVENTION
The present invention has the object of providing a circuit analysis tool having a function that enables the use of a high-accuracy simulator of SPICE2 or the like singly or together with a simulation function while reducing the time required for processing from the first simulation.
The present invention provides a first circuit analysis tool comprising: a storage section of circuit connection information of a semiconductor integrated circuit; a node state determining section that, when a specified signal is inputted to signal input terminals or internal nodes of the circuit specified by a circuit connection information stored in the storage section, determines at every node connected to terminals of circuit elements constituting the circuit whether or not potential of the node changes in accordance with a lapse of time; and an element deleting section that updates the circuit connection information so as to delete a circuit element provided with only a terminal connected to a node whose potential does not change in accordance with a lapse of time from the circuit specified by the circuit connection information stored in the storage section on the basis of a result of determination in the node state determining section and instead provide each node whose potential does not change with a terminal and attaches information for specifying the potential of the node that does not change in accordance with a lapse of time to each terminal provided.
The present invention provides a second circuit analysis tool, based on the first circuit analysis tool, further comprising: a designating means for designating an attentional node among the nodes inside the circuit specified by the circuit connection information stored in the storage unit; and a designated node protecting means for changing determination results of all the nodes connected to the terminals of the circuit element connected to the designated node to a node whose potential changes in accordance with a lapse of time when a circuit element connected to the node designated by the designating means exists among the circuit elements that have only terminals connected to the node whose potential is determined to be unchanged in accordance with a lapse of time in the node state determining section, wherein the element deleting section executes an element deleting process on the basis of a result of determination obtained after the processing in the designated node protecting means.
The present invention provides a third circuit analysis tool, based on the first or second circuit analysis tool, further comprising an output unit for displaying the circuit specified by the circuit connection information updated by the element deleting section.
The present invention provides a fourth circuit analysis tool, based on the third circuit analysis tool, wherein the output unit displays the result of determination in the node state determining section with regard to each node of the circuit to be displayed.
The present invention provides a fifth circuit analysis tool, based on the third or fourth circuit analysis tool, wherein the output unit further displays the circuit specified by the circuit connection information obtained before the updating executed by the element deleting section in a state in which the circuit can be discriminated from the circuit specified by the circuit connection information obtained after updating.
The present invention provides a sixth circuit analysis tool, based on any one of the first through fifth circuit analysis tools, further comprising a circuit analyzing means for executing a circuit analysis process on the basis of the circuit connection information updated in the element deleting section.
The present invention provides a seventh circuit analysis tool, based on the sixth circuit analysis tool, wherein the circuit connection information stored in the storage section is a net list described at the transistor level, and the circuit analyzing means has a circuit simulation function for executing a circuit simulation on the basis of the net list.
It is acceptable to provide a storage medium storing a program that makes a computer function as the first circuit analysis tool in order to solve the aforementioned problems.
It is also acceptable to provide a storage medium storing a program that makes a computer function as the first circuit analysis tool further provided with a circuit analyzing means for executing a circuit analysis process by means of the circuit connection information updated in the element deleting section.
The first circuit analysis tool of the present invention can reduce the amount of data of the circuit connection information by deleting the circuit element that exerts no influence on the circuit analysis process of the circuit simulation, the logical simulation and the like out of the circuit elements that constitute a circuit specified by the circuit connection information of the semiconductor integrated circuit during the design phase. By using the circuit connection information of the reduced amount of data, the high-accuracy circuit analysis process of SPICE2 or the like can be executed while reducing the time required for the processing from the beginning.
The second circuit analysis tool of the present invention can further prevent the possible deletion of the circuit element that has the terminal connected to the node designated by the operator (designer) in the aforementioned first simulation. This enables the obtainment of a circuit analysis result desired by the operator.
The third circuit analysis tool of the present invention further enables the con
Araki Yasuji
Nishida Kouji
Bowers Brandon
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Smith Matthew
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