Chipset supporting multiple CPU's and layout method thereof

Details Chipset supporting multiple CPU's and layout method thereof Chipset supporting multiple CPU's and layout method thereof

2005-04-05

2005-04-05

Elamin, A. (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S400000, C713S401000, C713S501000, C713S600000, C713S601000

Reexamination Certificate

active

06877102

ABSTRACT:
A chipset to support multiple CPU's and a layout method thereof. Those independent signal lines for delivering high frequency clock signals of the chipset are isolated from using by other signals without being multiplexed. Trace length of the independent signal line is shorter than that of the others. The spaces between the independent signal line and others are also larger than that between other signal lines. Signal transmission quality is significantly upgraded because the high frequency clock signal is not multiplexed and isolated from others.

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patent: 6590827 (2003-07-01), Chang et al.
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