Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-02-01
2002-12-31
Wong, Peter (Department: 2181)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S010000, C714S011000, C714S012000
Reexamination Certificate
active
06502209
ABSTRACT:
PRIORITY CLAIMED
This application claims the benefit of priority to Swedish Application No. 9801678-5 filed May 13, 1998, entitled Computer Chip And Apparatus With Enhanced Debug Capability.
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention generally relates to a computer chip and a computer apparatus, and more specifically to a computer chip and apparatus fully adapted to program debugging. It also relates to debugging system.
2. Technical Background
In developing new computer programs an important step is to debug the program in order to correct programming errors. Program debugging is performed by executing the program on a computer and monitoring different signals being communicated externally between the computer and peripherals as well as internally between different circuits of the computer. Such circuits are, for example, Central Processing Unit (CPU), Direct Memory Access (DMA) unit, main memory, and input/output (I/O) interface circuit. To be able to debug the program while the computer is running, conventionally for example a logic analyzer is connected by means of probes to the circuit board on which the computer circuits are mounted.
In order to speed up memory accesses, typically, a computer is provided with a cache memory. This memory is used, mainly by the CPU, as a fast, i.e. which has short access times, temporary memory, which holds only the most frequently and most recently used main memory addresses and data. A major part of all CPU main memory accesses are handled by merely the cache memory, and only a minor part incorporates the main memory by means of data exchange between the main memory and the cache memory. Thus, the communication between the CPU and the cache memory is central in the program execution and, therefore, is desirable to debug.
However, in modem computer construction there is an aim to integrate as many of the computer circuits as possible on a single chip. Typically, among others, both the CPU and the cache memory are integrated on the same chip, while the main memory is external to the chip though normally mounted on the same circuit board. The main memory normally is constructed from several interconnected chips. Due to the one chip integration it is not possible to monitor the communication between the CPU and the cache memory while debugging, but only between the CPU and the main memory.
Some different solutions to this problem have been tried. One prior art solution is to turn off the cache memory during the debugging operation. Thereby all memory accesses are made to the main memory and are able to be monitored. However, this means that one looses the possibility to monitor the program in true circumstances, and above all the execution rate is decreased. There are several types of erroneous behaviors that will not show under such circumstances. The cache handling is a crucial part of the operation of the program.
Another prior art solution is to manufacture a so called bondout chip, which is a special version of an ordinary chip, the special version chip having extra pins connected to internal buses of the chip. This is an expensive solution, since it requires manufacturing of a special chip parallel to the ordinary chip. Further, it causes the clock frequency to be decreased due to, among others, the extended leads. Thereby, a real-time debugging is not performed, which makes it possible for certain bugs causing errors in real-time execution to remain undetected.
Yet another prior art solution is to arrange certain registers providing for debug support. These registers, often referred to as breakpoint registers, permit the use of software breakpoints at predetermined points of the program execution. At the breakpoints current address and data information is loaded into the breakpoint registers to be read out by the monitoring system. This solution makes it possible to detect that the program execution has arrived safely at the breakpoints. However, a major drawback is that the debugging is not effected in real-time. Additionally, what happens between the breakpoints is not monitored.
Therefore there is a need for a new computer apparatus providing for monitoring also the communication between the CPU and the cache memory, the CPU and the cache memory being integrated on the same chip, while the computer is running at full clock rate.
An object of the present invention is to provide for monitoring the program execution to a greater extent than is possible in the prior art, while running the CPU at full clock rate, i.e. performing real-time debugging, and without providing a special version chip for debugging purposes.
SUMMARY OF THE INVENTION
In accordance with the invention, the object is achieved by a computer chip having integrated thereon a CPU and a cache system being interconnected, and at least one synchronization unit, said chip being setable in either one of at least two different running modes, a first one thereof being a device under test (DUT) mode, and a second one thereof being a MONITOR mode. The monitor mode is complementary to the DUT mode. The chip further comprises a debug bus connectable to another identical chip for communicating signals enabling the chip and said another chip to run in parallel while said chips are set in complementary modes. The signals comprise synchronization signals generated by said synchronization unit.
The computer chip, in this way being prepared for a debugging operation eliminates the excessive costs of producing a special version chip for debugging purposes. The debug bus and the synchronization circuit in combination provides for an efficient exchange of a small set of essential signals to another identical chip, which is set in MONITOR mode, i.e. debugging mode. The different modes are prepared for. Thus, a full rate debugging obtaining full information about the program execution is reachable.
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patent: 5434997 (1995-07-01), Landry et al.
patent: 5488688 (1996-01-01), Gonzales et al.
patent: 5491787 (1996-02-01), Hashemi
patent: 5491793 (1996-02-01), Somasundaram et al.
patent: 5809037 (1998-09-01), Mathewson
patent: 6131171 (2000-10-01), Whetsel
patent: 0313848 (1989-05-01), None
patent: WO 94/08313 (1994-04-01), None
Bengtsson Jan
Ranerup Kenny
Zander Per
Axis AB
Cary Charles C.
IP Creators
Vo Tim
Wong Peter
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