Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1998-12-08
2001-05-22
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S618000, C257S750000, C257S773000, C438S393000, C438S396000, C438S622000, C438S666000, C361S306100
Reexamination Certificate
active
06236102
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a chip type thin film capacitor which is used as a component for high frequency apparatuses, satellite communication system and the like. Particularly, the present invention relates to a chip type thin film capacitor and a manufacturing method therefor, in which the contact areas between inner electrodes and outer electrodes of the thin film capacitor are expanded, so that the defect rate of the product can be lowered, and the equivalent serial resistance can be also lowered.
2. Description of the Prior Art
In the generally known chip type thin film capacitor, the current situation is as follows. That is, when it is used as components of high frequency apparatuses or the satellite communication system, a relatively low equivalent serial resistance (ESR) and a high capacitance are required. Therefore, when it is manufactured, a lower electrode, a dielectric layer, and an upper electrode are formed upon a glass or ceramic substrate in the cited sequence. Then the electrodes are patterned to the required form, and then, a dielectric protecting layer is printed to protect the inner electrodes. Then an upper plate is made to stick on the dielectric protecting layer by using an epoxy resin, and outer electrodes are formed on the both sides of the structure, in such a manner that the upper and lower electrodes would be connected to the outer electrodes, thereby manufacturing a thin film capacitor having a low ESR value.
This is specifically illustrated in FIG.
1
. As shown in
FIG. 1
, a lower electrode
52
is formed upon a glass or ceramic substrate
51
in such a manner that a side face of the electrode
52
should be exposed. Then a dieectric layer
53
is formed upon the lower electrode
52
, and then, an upper electrode
54
is formed upon the dielectric layer
53
in such a manner that the opposite side face of the electrode
54
should be exposed.
Then the upper and lower electrodes
54
and
52
and the dielectric layer
53
are pattern to the required form. Then in order to protect the upper electrode
54
, a dielectric protecting layer
55
is printed upon the structure. Then an upper plate
56
is made to adhere on the dielectric protecting layer by using an epoxy resin adhesive. Then an electrolytic plating is carried out to form outer electrodes
58
on both side faces of the substrate
51
on which the upper and lower electrodes
54
and
52
have been formed.
Thus as shown in
FIG. 2
, by providing the dielectric layer
53
, one end of each of the upper and lower electrodes
54
and
52
is made to be connected to each of the outer electrodes
58
which have been formed on both side faces of the substrate
51
respectively. In this manner, the manufacture of the capacitor is completed.
In the above described conventional thin film capacitor, in order to obtain a relatively low ESR value, the contact areas between the upper and lower electrodes
54
and
52
and the outer electrodes
58
are increased. For this purpose, the both ends are ground or etched, so that the upper and lower electrodes
54
and
52
having a thickness of 2 &mgr;m or less would be exposed. Then the outer electrodes are coupled to them respectively, thereby increasing the contact areas between the two sets of the electrodes.
However, in the above described conventional chip type thin film capacitor, the upper and lower electrodes
54
and
52
having a thickness of 2&mgr; or less are ground or etched so that they would be exposed to the outside. Then the outer electrodes
58
are connected to the sides of them. Therefore, the outer electrodes
58
are connected only to the tips of the upper and lower electrodes
54
and
52
. Therefore, the areas of the inter-electrode connections are not sufficient. Further, during the electrolytic plating for connecting the outer electrodes
58
to the tips of the upper and lower electrodes
54
and
52
, the upper and lower electrodes
54
and
52
are liable to be short-circuited, thereby causing product defects. Further, the imperfect contact between the upper and lower electrodes
54
and
52
and the outer electrodes
58
degrades the product reliability, as well as lowering the yield.
Meanwhile, another thin film capacitor manufacturing method has been proposed in which a low ESR value is attained at a low cost.
This method is disclosed in U.S. Pat. No. 4,453,199, and is as shown in FIG.
3
. As shown in this drawing, upon an insulating substrate
100
made of glass or a ceramic material, there is deposited a thin film conductive layer
110
. Then the thin film conductive layer
110
which is an electrode is patterned into rows and columns, and then, a dielectric layer
130
is formed in such a manner that the entire surface of the thin film conductive layer
110
should be covered.
Then a plurality of discontinuous thin film conductive layers
140
are formed again on the dielectric layer
130
, in such a manner that the edges of the thin film conductive layers
140
should be exposed to the outside. Then an insulating layer
150
is formed to cover the entire surface of the thin film conductive layers
140
. Then the insulating substrate
100
is cut vertically, so that the edges of the thin film conductive layers
110
and
140
would be exposed. Then a terminal layer is formed, in such a manner that terminal electrodes should be electrically connected to the exposed portions of the thin film conductive layers
110
and
140
, thereby completing the manufacture of the thin film capacitor.
However, in the above described conventional chip type thin film capacitor, when the insulating substrate
100
is cut after the formation of the layers, the exposed edges of the thin film conductive layers
110
and
140
are extremely small. Therefore, when the outer terminal electrodes are formed, their contacts are very insufficient. Further, during the electrolytic plating for connecting the conductive layers
110
and
140
and the terminal electrodes together respectively, short circuits are formed between the conductive layers
110
and
140
, thereby causing product defects. Further, low ESR value cannot be obtained due to the insufficient contacts between the conductive layers
110
and
140
and the terminal electrodes.
SUMMARY OF THE INVENTION
The present invention is intended to overcome the above described disadvantages of the conventional techniques.
Therefore, it is an object of the present invention to provide a chip type thin film capacitor in which the contact areas between upper and lower electrodes (as inner electrodes) and outer electrodes contacted to the upper faces and side faces of the upper and lower electrodes are expanded so as to make it possible to obtain a low ESR value, and the formation of short circuits is prevented owing to the expanded contact areas between mentioned electrodes so as to prevent product defects and to stabilize the contacts between the inner and outer electrodes.
It is another object of the present invention to provide a method for manufacturing a chip type thin film capacitor, in which the contact areas between upper and lower electrodes (as inner electrodes) and outer electrodes contacted to the upper faces and side faces of the upper and lower electrodes are expanded so as to make it possible to obtain superior characteristics and to prevent the product defects.
In achieving the above objects, the chip type thin film capacitor according to the present invention includes: an insulating substrate; a thin film type conductive first electrode formed upon the insulating substrate starting from one edge of the substrate toward an opposite edge of it, and having a first outer electrode connection portion at an edge portion corresponding to an edge of the substrate; a first dielectric layer formed upon the first electrode, for insulating the first electrode; a second electrode formed upon the first dielectric layer starting from the opposite edge of the substrate to be overlapped with a portion of the first electrode, and having a se
Kim Young Min
Oh Bang Won
Renner , Otto, Boisselle & Sklar, LLP
Samsung Electro-Mechanics Co. Ltd.
Wojciechowicz Edward
LandOfFree
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