Chip to wiring interface with single metal alloy layer...

Details Chip to wiring interface with single metal alloy layer... Chip to wiring interface with single metal alloy layer...

2001-06-14

2003-06-03

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S750000, C257S751000, C257S763000, C257S764000, C257S765000, C257S770000, C257S771000, C438S612000, C438S618000, C438S633000, C438S687000

Reexamination Certificate

active

06573606

ABSTRACT:

FIELD OF THE INVENTION
The invention is directed to integrated circuit chips and wiring interconnect structures involving the metal copper, known as back end of the line (BEOL) structures, and in particular to a structure and process of forming an interface with a thin single alloy layer on copper interconnect metal in a semiconductor device that provides improved adhesion to subsequent deposited layers, protection against copper diffusion and resistance to electromigration and a lower interconnect dielectric constant.
BACKGROUND
In the fabrication of chip network circuitry involving the metal copper, interconnected to the vias and trenches of the network, those vias and trenches have been interconnected heretofore in the art through metalization type processes utilizing standard sequential procedures of thick dielectric deposition of such materials as SiO2 or low dielectric constant (K) materials, hardmask deposition, via and trench opening formation, deposition of thin liner film on via and trench walls, filling vias and trenches with copper metal, planarization of the top copper surface, and finally capping the top surface of the planarized copper with protective dielectric layers for preventing copper migration into the next upper dielectric layer which is usually of SiO2, Si3N4, or a capping type arrangement such as a multiple layer structure known in the art as BLOK, or other low dielectric constant (K) material, and, for minimizing interactions with the copper while the upper dielectric layer is deposited and processed. The final capping layer, further then can serve as a reactive ion etch stop layer for patterning a next upper dielectric layer. This procedure has come to be known in the art as “the integration scheme for Cu-BEOL”. The process is repeated for each subsequent level of the interconnect wiring. Heretofore in the art the capping layer has been quite thick and has resulted in excessive dielectric loss.
Thus far in the art, in chip network interconnections employing the metal copper, there have been interdependent considerations resulting from the possible electromigration of the copper and the adhesion properties of any layer that serves a capping function in the overall process and the thickness and properties of any capping layer on the dielectric constant of the interconnect. There has been some progress in the art heretofore.
In patent application Ser. No. 09/510,259, Filed Feb. 22, 2000, assigned to the assignee of this application, there is described a sequence of processes for forming dual protective layers made up of a bilayer metal cap/insulator (known as a BLOK layer in the art) that is positioned on the surface of Cu conductors of semiconductor devices to protect the Cu surface and to provide improved adhesion and reliability as layers are processed.
In patent application Ser. No. 09/361,573, Filed Jul. 27, 1999, assigned to the assignee of this application efforts in the control of electromigration through the control of the Cu/dielectric interface are advanced through using deposited surface films. There is a need in the art for capping layer, inter layer diffusion, adhesion and electromigration while maintaining high performance and reliability.
SUMMARY OF THE INVENTION
In the invention an electrically isolated copper interconnect structural interface is provided involving a single, about 50-300 A thick, alloy capping layer, that controls diffusion and electromigration of the interconnection components and reduces the overall effective dielectric constant of the interconnect; the capping layer being surrounded by a material referred to in the art as hard mask material that provides a resist for subsequent reactive ion etching operations, and there is also provided the interdependent process steps in the fabrication of the structural interface. The single layer alloy metal barrier in the invention is an alloy of the general type A—X—Y, where A is a metal taken from the group of cobalt (Co) and nickel (Ni), X is a member taken from the group of tungsten (W), tin (Sn), and silicon (Si), and Y is a member taken from the group of phosphorous (P) and boron (B); having a thickness in the range of 50 to 300 Angstroms with a preferable range being 50 to 75 Angstroms.


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Hu et al. “Reduced Electromigration and Stress Induced Migration of Cu Wires by Surface Coating” U.S. patent application Ser. No. 09/361,573 Filed Jul. 27, 1999.
Rubino et al. “Method for Forming Dual-Layer Low Dielectric Barrier for InterConnects and Device Formed”, U.S. patent application Ser. No. 09/510,259 Filed Feb. 22, 2000.

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