Chip-to-chip communication system using an ac-coupled bus...

Details Chip-to-chip communication system using an ac-coupled bus... Chip-to-chip communication system using an ac-coupled bus...

1999-08-16

2002-12-17

Myers, Paul R. (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S305000

Reexamination Certificate

active

06496889

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a chip-to-chip communication system. Chip-to-chip communication systems facilitate interactions between a number of devices. Typically the devices communicate with each other via a bus or a plurality of signal lines.
The term “chip-to-chip” refers to any implementation where a number of devices are inter-coupled together. The term “device(s)” is used to refer to one or more integrated circuits or cards which may include synchronous dynamic random access memories (SDRAM), double data rate (DDR) memories, micro-controllers, processors, memory modules, modem cards, and video cards, just to name a few. A memory system and computer system are ready examples of a chip-to-chip communication system formed from an inter-coupled group of integrated circuits or cards. The usage of the term “bus” refers to any arrangement of a plurality of conducting medium used to transport information between devices. Such conducting medium may be implemented in one of many ways including wires in a flex tape or patterned conducting lines on a printed circuit board, etc. For our purposes, one of a conducting medium used in a bus of a chip-to-chip communication system will hereinafter be referred to as a “signal line.”
Thus, in keeping with the foregoing, an example of a conventional chip-to-chip communication system is illustrated in FIG.
1
. Here, chip-to-chip communication system
10
includes master device
20
and a plurality of slave devices
30
a
to
30
n
, coupled by at least one signal line
40
. In this example, the master device
20
may be any device capable of communicating with one or more other master devices (not illustrated) or with slave devices
30
. Typically, slave devices
30
a-n
only respond to commands given by master device
20
, and do not communicate with each other. More specific examples of chip-to-chip communication systems include a memory system having a controller directing interactions with a number of memory devices over a bus, or a computer system having a mother board with a central processing unit (CPU) communicating with a number of peripheral device cards.
One common class of slave devices includes memory devices, such as dynamic random access memory (DRAM). Such devices are characterized by limited access speeds. Access speeds for conventional DRAMs have significantly lagged behind the operating speeds pioneered in conventional CPUs. Thus, designers face a constant challenge in the development of memory systems having sufficiently high data throughput to fully utilize CPU performance capability.
With reference to
FIG. 2
, a chip-to-chip communication system implemented as a conventional memory system
45
is illustrated. Here, a controller
50
and a number of memory devices
60
are disposed on a circuit board (not illustrated). The memory devices
60
are directly coupled in parallel to the controller
50
over a wide bus
70
. In this example, each memory device
60
has a dedicated portion of signal lines
80
directly coupled to the controller
50
. In more detail, each memory device
60
is coupled to eight signal lines and all sixty four signal lines of wide bus
70
are coupled to controller
50
.
It is well known that by utilizing this parallel approach to couple memory devices to the controller, the data throughput of the chip-to-chip communication system
45
may be improved. However, the width of the bus is limited by physical constraints, i.e., the available space and layout area of the circuit board. Thus, achieving additional data throughput by widening the bus (i.e., increasing the number of signal lines) has a maximum feasible limit.
Many different techniques have been employed in attempts to increase the data throughput of the conventional memory system. One attempt uses a relatively narrow bus and faster information transfer rates. “Information” in this context refers broadly to data, control and/or address information.
With reference to
FIG. 3
, a chip-to-chip communication system employing a relatively narrow bus is shown. In this example, a plurality of memory devices
105
, are directly coupled to a controller
110
via narrow bus
115
. Bus
115
comprises relatively few signal lines as compared to the parallel architecture of FIG.
2
. This later conventional approach does not utilize a parallel architecture to achieve high data throughput. Thus, physical constraints tend to be less of a concern. Rather, in this conventional approach, controller
110
and memory devices
105
incorporate high speed interfaces. Here, high data throughput is achieved by transferring information between the controller and the memory devices at high transfer rates.
As information transfer rates are increased over a signal line, difficulties arise which impose a practical upper limit on these higher rates. With reference to
FIG. 4A
, a chip-to-chip communication system is shown having a signal line
220
coupling a plurality of devices
230
a
to
230
c
. The plurality of devices
230
a
to
230
c
are “directly coupled ” to the signal line
220
at locations
240
a
to
240
c
. Two adjacent locations
240
a
and
240
b
span distance “d” to define a plurality of line segment
210
a
to
210
d
. Each line segment
210
a-d
may represent a common pitch between devices
230
a
to
230
c
. The term “directly coupled” refers to an electrical connection between a plurality of input/output (I/O) interface circuits
242
a
to
242
c
and signal line
220
.
In this example, one line segment
210
is a conductor which may be modeled by electrical elements as shown in line segment model
250
. The elements in the line segment model
250
describe the electrical behavior of each signal line segment. This electrical behavior is practically unnoticeable and therefore irrelevant at lower information transfer rates but becomes more significant to system performance as rates are increased. It is known to those skilled in the art that disposing a plurality of devices at equidistant points along a signal line causes the signal line to behave as multi pole low pass filter.
As the length “d” of the line segments
210
a-d
is decreased, the effective maximum operation frequency decreases. With reference to
FIG. 4B
, a representational graph of the signal line frequency response of the conventional chip-to-chip communication system with respect to three device I/O spacings is illustrated. Graph
410
depicts signal amplitude over a range of effective operation frequencies for signal line
220
(
FIG. 4A
) as a function of three device spacings d
1
, d
2
, and d
3
. Graph
410
illustrates three decreasing device I/O spacings d
1
, d
2
, and d
3
and correspondingly decreasing cutoff frequency curves
412
,
414
, and
416
.
With further reference to
FIG. 4A
, a plurality of “interface conductors”
255
a
to
255
c
typically couples each of interfaces
242
a
to
242
c
on devices
230
a
to
230
c
and signal line
220
. The term “interface conductor” denotes all structures coupled to interfaces
242
a
to
242
c
and the signal line at location
240
a
to
240
c
. For example, interface conductors
255
a-c
might include bond. wires, pins, modules or circuit card connectors, ball bonds, bond pads, electrostatic discharge protection devices, driver and receiver circuits and related interconnects. The interface conductors
255
a-c
, similar to the line segments
210
a-d
, may be modeled using electrical elements as shown in an interface conductor model
260
. The electrical elements in interface conductor model
260
generally describe electrical behavior associated with the interface conductor
255
.
When operating at high data transfer rates, the electrical behavior of the system depends, to a significant extent, upon the practical and physical attributes of the line segments
210
and the interface conductors
255
. Here, the line segment model
250
, includes inductive component
265
, capacitive components
270
and resistive components
275
. Interface conductor model
260
includes inductive component
280
, capac

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