Chip testing within a multi-chip semiconductor package

Details Chip testing within a multi-chip semiconductor package Chip testing within a multi-chip semiconductor package

2000-09-21

2004-05-04

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000, C702S108000, C438S014000

Reexamination Certificate

active

06732304

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the testing of semiconductor devices and, more particularly, to the testing of chips within a multi-chip packaged semiconductor device.
2. Related Art
Semiconductor devices have continually evolved to provide improvements such as miniaturization, increased speed, reduced power consumption, and reduced cost. As an example, memory is an essential part of an electronic system because it stores information required by the system, such as computational instructions, preliminary calculation data, temporary data, and various other data. Current semiconductor or integrated circuit (IC) memory devices can store large amounts of data in relatively small packages. Exemplary IC memory devices include random access memory (RAM) devices such as static RAM (SRAM), dynamic RAM (DRAM), non-volatile RAM (NVRAM), and read only memory (ROM) devices such as programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory.
FIG. 1
illustrates a conventional electronics system
100
comprising a printed circuit (PC) board
102
, a system IC
104
, and a number of memory devices
106
. PC board
102
may be a layered dielectric structure with internal and external wiring that allows system IC
104
and memory devices
106
to be mechanically supported and electrically connected internally to each other and to outside circuits and systems. Memory devices
106
are discrete ICs such as four DRAM ICs of 512 kilobits (Kb) by 32 bits, which may be combined to provide 512 Kb by 128 bits. System IC
104
may comprise, for example, a microprocessor or an application specific integrated circuit (ASIC) that utilizes memory devices
106
to store information. Each of memory devices
106
and system IC
104
may be separately packaged in a suitable package formed of polymer or ceramic and having a plurality of input/output (I/O) pins for connection to PC board
102
.
The arrangement of system
100
provides certain advantages, such as ready testing of system IC
104
and memory devices
106
prior to their connection to PC board
102
and easy removal and replacement of faulty discrete components. However, system
100
can be relatively large and may require more space than is available for many types of electronic devices such as cellular telephones, laptops, and personal digital assistants.
FIG. 2
is a block diagram of a conventional multi-chip module (MCM)
200
that integrates a number of raw chips (i.e., the silicon containing the integrated circuit—also referred to as a “die”) into a single semiconductor device. MCM
200
comprises a system chip
202
and a number of memory chips
204
on a substrate
206
. System chip
202
and memory chips
204
may correspond functionally to system IC
104
and memory devices
106
, respectively, of
FIG. 1
, but are provided within a single, discrete package. Relative to system
100
, MCM
200
provides certain advantages, such as a reduction in the amount of space required for implementation and an increase in processing speeds due to shorter leads between chips.
A multi-chip packaged semiconductor device may be viewed in terms of primary and secondary chips. A primary chip has direct access to external connectors of the multi-chip package and can communicate or convey information directly through these external connectors to components or devices external to the multi-chip package. For example, a primary chip may comprise an application specific integrated circuit (ASIC) controller or microprocessor that performs the main system functions of the multi-chip package. System chip
202
would also be an example of a primary chip.
A secondary chip generally does not have direct access to external connectors and typically is utilized in concert with the primary chip to assist or enhance the primary chip's performance or functionality. For example, a secondary chip may comprise a memory subsystem, co-processor subsystem, analog subsystem, or other application-type specific subsystem. Memory chips
204
would also be an example of secondary chips. Thus, secondary chips generally are not able to “talk” or communicate directly through external connectors.
A drawback of conventional multi-chip packaged semiconductor devices, such as MCM
200
, is that it does not allow complete testing of the secondary chips once they are incorporated into the package. For example, in MCM
200
, memory chips
204
are connected to system chip
202
, with system chip
202
connected to a number of I/O pins
208
of MCM
200
. No direct connections are available between memory chips
204
and external test equipment and, thus, a stringent final test of memory chips
204
within MCM
200
is not possible.
Typically, prior to packaging for an MCM, chips are tested using known good die (KGD) technology. There are various levels of KGD technology for die testing. These levels range from wafer level functional and parametric testing (i.e., wafer sort tests) to dynamic burn-in with full testing that continually tests the die while at high temperatures. The more a die is tested, the more likely an assembled MCM will function properly. However, even the most rigorous die testing prior to assembly will not guarantee that the assembled MCM will function as desired. For example, some chips may become damaged during assembly (i.e., after die testing) or the die connections may be faulty within the MCM.
With regard to MCM
200
, although is possible to test memory chips
204
by transferring data through other chips (e.g., system chip
202
), this type of testing fails to detect all of the various types of memory failures. Specifically, external integrated circuit test equipment does not have direct access to the secondary chips because there are no pin-outs or other direct connections, because secondary chips interface through the primary chips. Consequently, a number of MCM failures are the result of integrated circuit chips that have not been fully tested. Often, these failures are not discovered until after incorporation into an electronic device, which adds to the cumulative cost of the defective MCM, not only for the MCM manufacturer, but also for their customers whose products fail to function properly due to the defective MCM. Thus, for complete testing and for quality and reliability reasons, direct access to secondary chips is required.
As a result, there is a clear need for a system and method to test one or more chips of a multi-chip semiconductor package after integration into the chip packaging (e.g., MCM packaging).
SUMMARY OF THE INVENTION
The present invention provides a system and method that provides complete testing of one or more secondary chips within a multi-chip semiconductor device.
In accordance with an embodiment of the present invention, a packaged semiconductor device comprises a plurality of external connectors, a system chip connected to at least a first group of external connectors, and a memory chip connected to the system chip through a data bus. The memory chip comprises a plurality of data buffers, for transferring data between the memory chip and the data bus, and at least one test buffer connected to at least a first group of the data buffers. One or more test buffers are connected to certain of the first group of external connectors to provide testing of the memory chip while contained within the packaged semiconductor device.
In accordance with another embodiment of the present invention, a method of testing a memory within a packaged semiconductor device comprises providing a plurality of connectors on the packaged semiconductor device to connect to external components, system circuitry connected to a first group of the connectors, and memory circuitry connected to the system circuitry through a data bus. The memory circuitry further provides data buffers, for transferring data between the memory circuitry and the data bus, and at least one test buffer connected to a first group of the data buffers and conn

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