Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
1999-08-10
2001-12-18
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S676000, C257S680000, C257S684000, C257S711000, C257S731000
Reexamination Certificate
active
06331729
ABSTRACT:
TECHNICAL FIELD
This invention relates to a semiconductor packaging chip-supporting substrate, a process for producing the substrate, a semiconductor device making use of the substrate, and a process for fabricating the semiconductor device.
BACKGROUND ART
As semiconductors have become more highly integrated, the number of input-output terminals has increased. Accordingly, semiconductor packages having a large number of input-output terminals have become required. Input-output terminals are commonly grouped into a type where the terminals are arranged in a line on the perimeter of a semiconductor package and a type where they are arranged in lines not only on the perimeter but also in the inner area of a semiconductor package.
The former is typified by QFP (quad flat package). To make it have more terminals, terminal pitches must be made narrower. However, in a region of 0.5 mm pitch or less, a high-grade technique is required to connect terminals to a wiring board.
The latter array type enables arrangement of terminals at relatively large pitches, and hence is suited for multipin construction. As the array type, PGA (pin grid array), having connecting pins, has commonly been available. This, however, is of an insert type for its connection with a wiring board, and is not suited for face packaging. Accordingly, a package called BGA (ball grid array), which enables face packaging, has been developed.
Meanwhile, as electronic instruments are made compact, there is a stronger demand for making package size smaller. As a package that meets such a demand for smaller size, what is called a chip-size package (CSP) is proposed. This is a package having portions connecting with an external wiring substrate, not on the perimeter of a semiconductor chip but in its packaging region. As specific examples, it includes those in which a polyimide film with bumps is bonded to the surface of a semiconductor chip so as to make electrical interconnection with the chip through gold lead wires, followed by potting of epoxy resin or the like to effect encapsulating (NIKKEI MATERIALS & TECHNOLOGY 94.4, No. 140, pp.18-19), and those in which metal bumps are formed at positions corresponding to portions where a semiconductor chip connects with an external wiring substrate, and the semiconductor chip is face-down bonded, followed by transfer molding on a provisional substrate (Smallest Flip-chip-like Package CSP; The Second VLSI Packaging Workshop of Japan, pp.46-50, 1994).
However, it does not mean that most semiconductor packages hitherto proposed are small-sized and adaptable to high integration and also to be preventive of package cracking and have a superior reliability and yet to have a superior productivity.
DISCLOSURE OF THE INVENTION
The present invention provides a semiconductor packaging chip-supporting substrate that can prevent package cracking and make it possible to produce a small-sized semiconductor package having a superior reliability, a semiconductor device making use of such a substrate, and processes for producing them.
The semiconductor packaging chip-supporting substrate of the present invention comprises:
A. an insulating supporting substrate on one surface of which at least two wirings having semiconductor chip mount areas are so formed as to be disposed in such a way that, when a semiconductor chip is mounted at the semiconductor chip mount areas of the wirings, an empty space is formed by the bottom surface of the semiconductor chip, the side surfaces of the wirings and the surface of the insulating supporting substrate;
B. at least one through-hole formed in the insulating supporting substrate at its part facing the empty space; and
C. an insulating film adhesive material formed at a semiconductor chip mount region where the semiconductor chip is to be mounted, inclusive of the semiconductor chip mount areas of the wirings;
the insulating film adhesive material being an insulating film adhesive material having a Tg (glass transition temperature) of 100° C. or above and a residual volatile component of 2.0% (weight by weight) or less at least at the stage where the semiconductor chip is mounted via the insulating film adhesive material.
In the present invention, the insulating film adhesive material having a Tg of 100° C. or above and a residual volatile component of 2.0% (weight by weight) or less may be formed at the semiconductor chip mount region. Alternatively, an insulating film adhesive material having a Tg of 80° C. or above and a residual volatile component of 15.0% (weight by weight) or less may be formed at the semiconductor chip mount region and then the insulating film adhesive material may be subjected to heat treatment at a stage prior to the stage where the semiconductor chip is mounted via the insulating film adhesive material, to make the insulating film adhesive material have a Tg of 100° C. or above and a residual volatile component of 2.0% (weight by weight) or less.
In a preferred embodiment, the semiconductor packaging chip-supporting substrate of the present invention comprises:
A′. an insulating supporting substrate on one surface of which at least two wirings having inner-connecting areas for making connection with semiconductor chip electrodes and semiconductor chip mount areas are so formed as to be disposed in such a way that, when a semiconductor chip is mounted at the semiconductor chip mount areas of the wirings via an insulating film adhesive material, an empty space is formed by the surface of the insulating film adhesive material on its side facing the insulating supporting substrate, the side surfaces of the wirings and the surface of the insulating supporting substrate;
B′. openings provided in the insulating supporting substrate at its part on which the wirings are formed and at which outer-connecting areas conducting to the inner-connecting areas are provided;
C′. at least one through-hole formed in the insulating supporting substrate at its part facing the empty space; and
D′. an insulating film adhesive material formed at a semiconductor chip mount region where the semiconductor chip is to be mounted, inclusive of the semiconductor chip mount areas of the wirings;
the insulating film adhesive material being an insulating film adhesive material having a Tg of 100° C. or above and a residual volatile component of 2.0% (weight by weight) or less at least at the stage where the semiconductor chip is mounted via the insulating film adhesive material.
The present invention also provides a process for producing a semiconductor packaging chip-supporting substrate, the process having the following steps (1) to (3):
(1) A through-hole forming step of forming a through-hole in an insulating supporting substrate;
(2) a wiring forming step of forming on one surface of the insulating supporting substrate at least two wirings having semiconductor chip mount areas, so formed as to be disposed in such a way that, when a semiconductor chip is mounted at the semiconductor chip mount areas of the wirings, an empty space is formed by the bottom surface of the semiconductor chip, the side surfaces of the wirings and the surface of the insulating supporting substrate; and
(3) an adhesive layer forming step of forming an insulating film adhesive material having the above properties, at a semiconductor chip mount region where the semiconductor chip is to be mounted, inclusive of the semiconductor chip mount areas of the wirings.
The adhesive layer (insulating film adhesive material) may be formed by, e.g., attaching the insulating film adhesive material having the above properties [i.e., a glass transition temperature of 100° C. or above and a residual volatile component of 2.0% (weight by weight) or less] to the semiconductor chip mount region. Alternatively, it may be formed by forming previously (e.g., by attaching a film) an insulating film adhesive material having a glass transition temperature of 80° C. or above and a residual volatile component of 15.0% (weight by weight) or less, at the semiconductor chip mount region
Ichimura Shigeki
Inoue Fumio
Kato Toshihiko
Yusa Masami
Abraham Fetsum
Hitachi Chemical Company Ltd.
Pennie & Edmonds LLP
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