Chip structure with arrangement of side pads

Details Chip structure with arrangement of side pads Chip structure with arrangement of side pads

2006-04-12

2008-11-11

Andújar, Leonardo (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

C257SE23079

Reexamination Certificate

active

07449788

ABSTRACT:
A chip structure includes a substrate with at least an arrangement of side pads on an active surface of the substrate and adjacent to one side of the active surface. The arrangement of side pads includes an outer pad row, a middle pad row and an inner pad row disposed along the extension direction of the side. The middle pad row is further away from the side than the outer pad row. The inner pad row is further away from the side than the middle pad row. Pads of the middle pad row and pads of the inner pad row are staggered. One non-signal pad of the middle pad row is located between two adjacent signal pads of the inner pad row, and one non-signal pad of the inner pad row is located between two adjacent signal pads of the middle pad row.

REFERENCES:
patent: 6861740 (2005-03-01), Hsu
patent: 6935870 (2005-08-01), Kato et al.

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