Chip stacking structure

Details Chip stacking structure Chip stacking structure

2006-11-29

2009-02-24

Williams, Alexander O (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257SE23031, C257SE23052, C257SE23002, C257S774000, C257S666000, C257S698000, C257S723000, C257S777000, C257S696000, C257S784000, C257S786000, C257S775000, C257S776000, C257S680000

Reexamination Certificate

active

07495327

ABSTRACT:
An efficient chip stacking structure is described that includes a leadframe having two surfaces to each of which can be attached stacks of chips. A chip stack can be formed by placing a chip active surface on a back surface of another chip. Electrical connections between chips and leads on the leadframe are facilitated by bonding pads on chip active surfaces and by via that extend from the bonding pads through the chips to the back surfaces.

REFERENCES:
patent: 6080931 (2000-06-01), Park et al.
patent: 7217995 (2007-05-01), Tsai et al.
patent: 2004/0080040 (2004-04-01), Dotta et al.

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