Chip stacking by edge metallization

Details Chip stacking by edge metallization Chip stacking by edge metallization

1997-01-17

1998-10-06

Whitehead, Jr., Carl W.

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

257686, 257777, 257718, 257720, H01L 2310

Patent

active

058181075

ABSTRACT:
An integrated circuit package derives increased mechanical robustness and electrical reliability consistent with increased heat dissipation capacity by bonding of integrated circuit chips into a chip stack and bonding the chip stack onto a substrate such as a chip, board, module or another integrated circuit by forming a solder or conductive adhesive bond between a bonding/contact pad on the substrate and a metallization feature extending at least on limited opposing areas of major surfaces of the chip and across the edge of the chip. Thickness of the metallization feature and bonding material provides a "stand-off" between chips allowing improved heat dissipation by fluid flow, conduction through a viscous thermally conducting material and/or a heat sink disposed between chips in the stack. Novel techniques of forming a metallization feature across the edge of a chip with high efficiency and manufacturing yield includes enclosure of chips or strips of chips in a tool including a grooved mask or enclosing the chips or strips of chips in a resist which may be exposed and developed using at least a portion of the same tool. An application provides a package including heat sinking of a microprocessor master chip in combination with stack of slave chips as memory, logic macros, cross-bar switches and the like which may also include heat sinks between chips in each chip stack.

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