Chip stack package and method of fabricating the same

Details Chip stack package and method of fabricating the same Chip stack package and method of fabricating the same

2011-05-24

2011-05-24

Menz, Douglas M (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S773000

Reexamination Certificate

active

07948089

ABSTRACT:
A chip stack package is provided, wherein semiconductor chips having different die sizes are stacked by arranging pads in a scribe region through a redistribution process, so that the thickness of the package can be reduced. A method of fabricating the chip stack package is also provided. In the chip stack package, a plurality of circuit patterns are arranged on one surface of a substrate, and a unit semiconductor chip is mounted thereon. The unit semiconductor chip includes a plurality of semiconductor chips sequentially stacked on the substrate. The semiconductor chips of the unit semiconductor chip have different die sizes. One of the semiconductor chips includes a plurality of first pads arranged in a first chip region, and the other semiconductor chips include second pads arranged in a scribe region at an outside of a second chip region defined by the scribe region.

REFERENCES:
patent: 6691696 (2004-02-01), Akram et al.
patent: 6731013 (2004-05-01), Juso et al.
patent: 7326592 (2008-02-01), Meyer et al.
patent: 2006/0220262 (2006-10-01), Meyer et al.
patent: 2003-163327 (2003-06-01), None
patent: 2002-0047746 (2002-06-01), None
patent: 10-2005-0021078 (2005-03-01), None
English language abstract of Japanese Publication No. 2003-163327.
English language abstract of Korean Publication No. 10-2005-0021078.

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