Chip stack, chip stack package, and method of forming chip...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings

Reexamination Certificate

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Details

C257S685000, C257S777000, C257SE25006, C257SE25013, C257S025000, C257SE25021, C257SE25027, C438S109000

Reexamination Certificate

active

07964948

ABSTRACT:
A chip stack may include a first chip and a second chip stacked on the first chip. Each of the first and second chips may include a substrate having an active surface and an inactive surface opposite to the active surface; an internal circuit in the active surface; an I/O chip pad on the active surface and connected to the internal circuit through an I/O buffer; and a I/O connection pad connected to the I/O chip pad through the I/O buffer by a circuit wiring. A redistributed I/O chip pad layer may be on the active surface of the first chip, the redistributed I/O chip pad layer redistributing the I/O chip pad. The I/O connection pads of the first chip and the second chip may be electrically connected to each other by an electrical connecting part.

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patent: 10-2004-0091580 (2004-10-01), None

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