Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-11-09
2001-09-18
Clark, S. V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S783000, C257S778000, C257S787000, C438S108000, C438S127000
Reexamination Certificate
active
06291884
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor packages, and more particu- larly, to the production of chip-size ball grid array (“BGA”), land grid array (“LGA”), and lead-less chip carrier (“LCC”) semiconductor packages.
2. Description of the Related Art
Currently, ball grid array (“BGA”), land grid array (“LGA”), and lead-less chip carrier (“LCC”) packages for integrated circuit (“IC”) dies, or “chips,” are widely used in the semiconductor packaging industry. Because these types of packages use area array contacts instead of conventional perimeter leads, the physical size of relatively high-pin-count packages can be significantly reduced. However, the relatively large pitch size present in conventional BGAs, LGAs and LCCs requires large package bodies to accommodate applications having high input/output terminal (I/O) requirements. To further reduce the size of the packages and yet accommodate high I/O applications, so-called “chip-size,” or “chip-scale” (as well as “near-chip-size,” or “near-chip-scale”) semiconductor packages, including BGA, LGA and LCC types of such packages, i.e., packages that are the same (or nearly the same) size as the IC chip packaged therein, have recently been developed. Indeed, a “rule-of-thumb” for characterizing the size of such packages has developed within the industry -packages that have the same area, or an area that is up to a maximum of 20% greater than that of the chip, are characterized as “chip-size,” whereas, packages having an area that is more than 20% greater than the area of the chip are characterized as “near-chip-size.”
In “Reliable BGAs Emerge In Micro Form,”
Electronic Engineering Times
p. 104, 111 (September 1994), T. H. DiStefano discusses a near-chip-size, “micro-BGA” (“&mgr;BGA”) type of package developed by Tessera, Inc.
FIG. 1
is a cross-sectional view of a similar BGA package
11
. In
FIG. 1
, an IC chip
10
has a plurality of bonding pads
12
on the margin of its upper surface. The bonding pads on the chip are connected to a plurality of metallizations, or conductive traces
16
, on a flexible insulative substrate
14
(typically a polyimide resin tape) by electrical connectors
18
. A conductive bump
20
is formed on each trace
16
to enable electrical connections between the &mgr;BGA
11
and other electrical components, e.g., a main, or “mother” board (not illustrated).
A compliant elastomeric layer, or “interposer,”
15
is located between the chip
10
and the substrate
14
. The layer
15
is attached directly to the face
22
of the chip
10
with, e.g., a layer of a silicon-based adhesive
19
. The chip
10
, in turn, is bonded to a “thermal spreader”
26
using a layer of adhesive
24
. The connectors
18
are encapsulated with a flexible, protective resin (silicone) envelope to complete the fabrication of the &mgr;BGA package
11
. Various examples of such types of packages may be found in U.S. Pat. Nos.: 5,398,863 to G. W. Grube et al.; 5,258,330 to I. Y. Khandros et al.; 5,148,266 to I. Y. Khandros et al.; and, 5,148,265 to I. Y. Khandros et al.
Importantly, in such conventional packages, the elastomeric layer
15
serves to compensate for the large difference in the respective thermal coefficients of expansion (TCE) of the chip
10
and the substrate
14
. Such compensation is necessary because the substrate
14
, which is typically formed of a flexible polyimide (e.g., Capton) tape or film (TCE ≈15-18 parts-per-million per degree Centigrade (PPM/° C.)), experiences a much greater amount of thermal expansion and contraction with heating and cooling, respectively, than does the chip
10
, which is typically made of silicon (TCE=4 PPM/° C.) or other semiconductor material. By accommodating the TCE mismatch, the elastomeric layer
15
provides protection against stress-related problems in the packages, such as warping and solder ball cracking, caused by this disparity. However, the elastomeric layer
15
also comprises an additional element in the package and involves additional processing steps in the fabrication thereof, which not only increases both the cost and the thickness of the package, but reduces its heat transfer capabilities, as well.
Also of importance, the chip
10
is typically sawn from the semiconductor wafer in which it is formed before it is incorporated into the conventional BGA package
11
. In a conventional fabrication process, many identical chips are integrally formed simultaneously in a semiconductor wafer using known photolithography techniques. Each individual circuit is tested while still integral to the wafer, and defective chips are inked or otherwise electronically marked as such. Each chip is then cut from the wafer, the defective chips are discarded, and the good chips are incorporated into individual packages. However, processing each chip individually increases the amount of handling required, and hence, packaging costs.
It is therefore desirable to simplify the manufacturing process and reduce the packaging costs of such packages by developing a wafer-scale packaging process wherein a plurality of chips are simultaneously packaged while still joined together in a wafer, i.e., before they are separated from it. It is further desirable to simplify BGA, LGA and LCC package manufacture by eliminating the need for an additional elastomeric layer to accommodate the TCE mismatch between the chip and its substrate, yet do so in a package that is not subject to temperature-related stress problems. It is also desirable to reduce the size of the packages to that of the chip itself.
BRIEF SUMMARY OF THE INVENTION
This invention provides a wafer-level manufacturing process for fabricating chip-size BGA (CS-BGA), LGA (CS-LGA) and LCC (CS-LCC) semiconductor packages that are immune to temperature-induced stress problems without need for an elastomeric interposer.
In one preferred embodiment of the invention, the bottom surface of a rigid, electrically insulative substrate is mounted to the top surface of a chip in a semi-conductor wafer by means of an adhesive. Importantly, the material of the substrate is chosen such that its TCE is the same, or nearly the same, as that of the underlying chip.
In this first embodiment, the substrate has an area that is somewhat less than that of the chip, and is mounted in the center of the chip such that its edges are inboard of the edges of the chip to expose bonding pads on the periphery of the underlying chip. By mounting the rigid substrate such that the first terminals are confined within the area of the chip, the resulting BGA, LGA or LCC package is “chip sized,” i.e., has an area substantially equal to that of the chip itself.
In the first embodiment, first terminals of conductive traces, preferably copper or tungsten, either thick-film or thin-film, which are formed on the top surface of the substrate, are then electrically connected to corresponding conductive pads on the periphery of the top surface of the chip by fine, conductive bonding wires. After wire bonding, the regions containing the first terminals on the substrate, the pads on the chip, and the bonding wires are encapsulated with a protective epoxy resin, which is accomplished by dispensing a bead of epoxy having a relatively high viscosity over the pads on the chip, the bonding wires and the first terminals on the substrate to completely cover them, then curing the encapsulant.
In a second, so-called “flip-chip” embodiment, the bottom surface of a rigid, electrically insulative substrate is mounted on the top surface of the chip. As in the first, wire-bonded embodiment, the material of the substrate is chosen such that its TCE is the same, or nearly the same, as that of the underlying chip.
First conductive terminals formed on the bottom surface of the rigid substrate are then electrically connected directly to corresponding conductive pads on the top surface of the chip by fusing balls of a conductive metal disposed between the first terminals and the pads, which also serves to attach the substrate to the ch
Glenn Thomas P.
Hollaway Roy D.
Amkor Technology Inc.
Clark S. V.
Lawrence Don C.
Skjerven Morrill & MacPherson LLP
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