Chip size package with stress relieving internal terminal

Details Chip size package with stress relieving internal terminal Chip size package with stress relieving internal terminal

2003-05-20

2004-11-02

Lee, Eddie (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Encapsulated

With specified encapsulant

C257S784000, C257S690000

Reexamination Certificate

active

06812581

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2002-148049 filed on May 22, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated device and a method for manufacturing a semiconductor integrated device, and more particularly, to a semiconductor integrated device having a packaging structure and a method for manufacturing such a semiconductor integrated device.
Packaging technology is important for reducing the size of a semiconductor integrated device.
FIGS. 1A and 1B
show a semiconductor integrated device
1
, which is a chip size package (CSP) employing packaging technology.
With reference to
FIG. 1A
, the semiconductor integrated device
1
includes a silicon substrate
10
and two glass substrates
20
and
30
. The silicon substrate
10
has an upper surface on which integrated circuits, which are semiconductor devices, are configured. The glass substrate
20
is adhered to the upper surface of the silicon substrate
10
by epoxy resin
21
. The glass substrate
30
is adhered to the lower surface of the silicon substrate
10
by epoxy resin
31
. The silicon substrate
10
and the glass substrate
30
have diagonal side surfaces.
A plurality of bumps
40
are arranged as external terminals on the bottom surface of the glass substrate
30
. A plurality of external wires
41
electrically connect the bumps to the integrated circuits configured on the silicon substrate
10
. A protection film
42
covers the external wires
41
, the epoxy resin
31
, the glass substrate
30
, and the portions surrounding the bumps
40
.
FIG. 1B
is a bottom view of the semiconductor integrated device. As shown in
FIG. 1B
, the bumps are arranged in a matrix-like manner on the bottom surface of the glass substrate
30
to configure a ball grid array (BGA).
FIG. 2A
is a cross-sectional view showing an external wire
41
and its surroundings. As shown in
FIG. 2A
, a silicon oxide film (SiO
2
)
12
is applied to the silicon substrate
10
. An internal pad (internal terminal)
14
and a silicon nitride film (Si
3
N
4
)
13
, which is adjacent to the internal pad
14
, is formed on the silicon oxide film
12
. The external wire
41
electrically connects the internal pad
14
to the bumps
40
. An internal wire
15
is formed on the silicon nitride film
13
to electrically connect the internal pad
14
to the integrated circuits on the silicon substrate
10
.
The internal pad
14
includes two metal layers
14
a
and
14
b
. The first metal layer
14
a
is formed on the silicon oxide film
12
. The second metal layer
14
b
is formed on the first metal layer
14
a
.
FIG. 2B
is a plan view showing the periphery of the internal pad
14
. The width W
14
of the internal pad
14
is greater than the width W
15
of the internal wire W
15
. Thus, the external wire
41
is connected to the internal pad
14
with a relatively low resistance.
As shown in
FIG. 2A
, the internal wire
15
is covered by a silicon oxide film (SiO
2
)
16
. Epoxy resin
21
adheres the silicon oxide film
16
and the glass substrate
20
together.
Temperature increase or moisture expands the materials forming the semiconductor integrated device
1
and produces stress. The degree of the stress differs in accordance with differences in the expansion coefficient of the materials.
For example, when the temperature of the semiconductor integrated device
1
changes, the volumes of the epoxy resins
21
and
31
, the expansion coefficients of which are relatively large, change significantly. The stress resulting from the volume change of the epoxy resin
31
is applied to the internal pad
14
and the internal wire
15
. More specifically, a temperature increase expands the epoxy resin
31
and produces stress resulting from the difference between the expansion coefficients of the epoxy resin
31
and the internal pad
14
. The stress acts on the internal pad
14
outwardly along the surface of the silicon substrate
10
, that is, toward the external wire
41
. A temperature decrease contracts the epoxy resin
31
and produces stress acting on the internal pad
14
inwardly along the surface of the silicon substrate
10
, that is, away from the external wire
41
.
Stress is applied in a concentrated manner to certain sections of the internal wire
15
. With reference to
FIG. 3
, which is a diagram illustrating an example of the stress, stress concentration will now be described. The epoxy resin
31
expands and contracts more than-the silicon substrate. Thus, the internal pad
14
expands and contracts so as to follow the expansion and contraction of the epoxy resin
31
. The internal pad
14
is represented by spring SP in FIG.
3
. Stress resulting from the expansion and contraction of the epoxy resin
31
concentrates in the proximity of the boundary between the silicon substrate
10
and the epoxy resin
31
, that is, in region B, which is encircled by the broken lines in FIG.
3
. Repetitive application of stress causes fatigue of the internal wire
15
. This may break the internal wire
15
and cause an abnormality of the semiconductor integrated device.
A filler may be mixed with the epoxy resin
31
to decrease the expansion coefficient. However, the expansion coefficient is still greater than that of the silicon substrate
10
even if a filler is mixed with the epoxy resin
31
. Accordingly, this does not solve the problem caused by the difference between expansion coefficients.
SUMMARY OF THE INVENTION
One aspect of the present invention is a semiconductor integrated device including an insulative substrate having a first substrate surface, on which a plurality of external terminals are configured, and a second substrate surface, which is opposite to the first substrate surface. A semiconductor chip has a first chip surface, on which a plurality of semiconductor devices are configured, a second chip surface, which is opposite to the first chip surface, and a side surface, which connects the first chip surface and the second chip surface. The second chip surface is opposed to the second substrate surface. Resin covers the side surface of the semiconductor chip and is applied between the second substrate surface and the second chip surface. The resin has an outer surface covering the side surface of the semiconductor chip. A plurality of external wires are formed along the outer surface of the resin and are electrically connected to the external terminals. A plurality of internal terminals are each connected to the external wires and relatively narrow internal wires. Each internal terminal extends above and across a boundary between the resin and the side surface of the semiconductor chip.
A further aspect of the present invention is a method for manufacturing a semiconductor device. The method includes forming an internal terminal on a first surface of a semiconductor wafer from which a plurality of semiconductor chips are fabricated so as to extend across a boundary between two adjacent semiconductor chips of the plurality of semiconductor chips, and etching a second surface of the semiconductor wafer that is opposite to the first surface along the boundary to expose a surface of the internal terminal. The exposed surface includes side surfaces of the semiconductor chips. The method further includes forming a resin layer to cover the second surface and exposed surface of the semiconductor wafer, adhering an insulative substrate to the second surface of the semiconductor wafer with the resin layer, forming a plurality of external terminals on the insulative substrate, cutting at least the insulative substrate, the resin layer, and the internal terminal along the boundary, forming an external wire connecting a cross section of the exposed internal terminal to the external terminals, and cutting out a plurality of semiconductor integrated devices from the semiconductor wafer by dividing the semiconductor w

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