Chip-size package structure and method of the same

Details Chip-size package structure and method of the same Chip-size package structure and method of the same

2007-07-03

2007-07-03

Potter, Roy Karl (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S108000

Reexamination Certificate

active

10973557

ABSTRACT:
The method includes a step of picking and placing standard good dice on a base for obtaining an appropriate and wider distance between dice than the original distance of dice on a wafer. The method of the chip-size package comprises the steps of separating dice on a wafer and picking and placing the dice on a base and filling a first material layer on the base into a space among the dice on the base. A dielectric layer with first openings is patterned to expose a portion of a conductive line of the dice. A conductive material is filled into the first openings and on the dielectric layer. Subsequently, a second material layer is formed to have a second openings exposing the conductive material and then welding solder balls on the second openings.

REFERENCES:
patent: 6002178 (1999-12-01), Lin
patent: 6013953 (2000-01-01), Nishihara et al.
patent: 6043109 (2000-03-01), Yang et al.
patent: 6389689 (2002-05-01), Heo

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