Chip-size package structure and method of the same

Details Chip-size package structure and method of the same Chip-size package structure and method of the same

2008-03-04

2008-03-04

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

C257S737000

Reexamination Certificate

active

07339279

ABSTRACT:
The method includes a step of picking and placing standard good dice on a base for obtaining an appropriate and wider distance between dice than the original distance of dice on a wafer. The method of the chip-size package comprises the steps of separating dice on a wafer and picking and placing the dice on a base and filling a first material layer on the base into a space among the dice on the base. A dielectric layer with first openings is patterned to expose a portion of a conductive line of the dice. A conductive material is filled into the first openings and on the dielectric layer. Subsequently, a second material layer is formed to have a second openings exposing the conductive material and then welding solder balls on the second openings.

REFERENCES:
patent: 5239198 (1993-08-01), Lin et al.
patent: 5629835 (1997-05-01), Mahulikar et al.
patent: 177766 (2003-09-01), None

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