Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2002-07-30
2003-09-16
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S780000
Reexamination Certificate
active
06621164
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device and a method for manufacturing the semiconductor devices, and more particularly to a chip size package having a concave pattern in bump pad and a method for manufacturing the same.
2. Description of the Related Arts
The electronic industry has been progressing with the miniaturization of electronic devices. This trend influences semiconductor packaging technology, which enables the connection between bare IC chips and other components. Typically, a semiconductor package has a footprint much larger than that of the chip. To adapt to the miniaturization trend, the size difference between the package and the chip has been reduced, producing a new package type called a Chip Scale Package (or a Chip Size Package) (CSP). Among the manufacturing technologies for the CSPs is Wafer Level Chip Scale Packaging, which assembles CSPs at the wafer level, rather than separately processing individual chips. The WLCSPs use a redistribution or a rerouting technology, which moves wiring attachment points from the electrode pads on the chip to other terminal pads. An external connection terminal such as a solder bump is formed on each redistributed terminal pad.
FIG. 1
schematically shows a semiconductor wafer
10
, which includes integrated circuit chips
20
and scribe lines
14
dividing the chips
20
. As shown in
FIG. 2
, which is an enlarged view of portion A of
FIG. 1
, chip pads
22
are on each chip
20
, and a passivation layer
24
covers the upper surface of the IC chip
20
except where openings through the passivation layer
24
expose the chip pads
22
.
Referring to
FIGS. 3 and 4
, in conventional wafer level chip scale packaging, a dielectric layer
34
and solder bumps
36
are formed on the surface of the wafer
10
. The solder bumps
36
electrically connect to the chip pads
22
of FIG.
2
. Then, a sawing apparatus is used to separate the wafer
10
along the scribe lines
14
, producing individual chips
30
.
FIG. 4
illustrates the cross-sectional structure of the CSP
30
. The solder bump
36
connects the chip pad
22
through a redistribution pattern
33
, and a first and a second polymer layer
31
and
34
, respectively, under and on the redistribution pattern
33
. Integrated circuits (not shown) are under the chip pad
22
and the passivation layer
24
. In the fabrication of the CSPs
30
on the wafer
10
, the first polymer layer
31
for the stress buffering and the electrical insulation is formed and patterned on the wafer
10
such that openings in the first polymer layer
31
expose the chip pads
22
. Under barrier metal (UBM)
32
is deposited on the chip pad
22
and first polymer layer
31
. Then, the redistribution pattern
33
is formed on the UBM
32
, and the second polymer layer
34
is formed on the redistribution pattern
33
such that the openings in the second polymer layer
34
expose a portion of the redistribution pattern
33
. Finally, UBM
35
and the solder bump
36
are formed on the exposed portion of the redistribution pattern
33
.
The CSP
30
is attached to an external substrate such as a printed circuit board through a plurality of the solder bumps
36
.
FIGS. 5 and 6
illustrate how a solder joint can develop cracks. As shown in
FIG. 5
, a solder joint
42
binds the package
30
to a substrate
40
. As known well, due to the dissimilarity of the coefficients of thermal expansion (CTE) between the chip constituting the package
30
and the substrate
40
, changes in temperature create shearing stress F on the solder joint
42
, as shown in FIG.
6
. The shearing stresses often cause cracks
46
or delamination
44
of the solder joint
42
.
SUMMARY OF THE INVENTION
The present invention is directed to chip size packages and methods for manufacturing the chip size packages. The method fabricates multiple chip size packages on a semiconductor wafer including integrated circuits, and separates the chip size packages by sawing.
In accordance with one aspect of the present invention, a semiconductor device is provided which comprises a semiconductor integrated circuit chip having a semiconductor substrate, a plurality of chip pads positioned on a surface of the semiconductor substrate, a passivation layer positioned on said surface of the semiconductor substrate, with the passivation layer including openings to expose said chip pads. A first polymer layer is formed on the passivation layer, with the first polymer layer having a first plurality of openings for exposing said chip pads. A patterned first barrier metal layer formed on the chip pads and the first polymer layer. A plurality of electrically conductive redistribution patterns are formed on the first barrier metal layer, each of said redistribution patterns including a bump pad area which includes a concave pattern, and a chip pad contact portion which is electrically connected to an associated chip pad.
The semiconductor device according to the above aspect further comprises a second polymer layer formed on the first polymer layer and said plurality of redistribution patterns, said second polymer layer having a plurality of openings, one for each bump pad area. A second barrier metal layer is formed on each of said redistribution patterns and a solder bump is positioned on each of the bump pad areas extending into the concave pattern at the bump pad area.
The semiconductor device according to the above aspect includes a third barrier metal layer positioned in each of said bump pad areas, the third barrier metal layer being interposed between the second barrier metal layer and a portion of the solder bump.
In accordance with another aspect of the invention, a method for manufacturing semiconductor devices is provided. The method comprises providing a semiconductor wafer having a semiconductor substrate including a plurality of chip pads; applying a passivation layer on the semiconductor substrate, and providing openings in said passivation layer to expose said chip pads; forming a first polymer layer on the passivation layer; forming a first barrier metal layer on the chip pads and the first polymer layer; forming a plurality of redistribution patterns on the first barrier metal layer, each redistribution pattern having a portion connected to the chip pads and having a bump pad area; and forming a concave pattern in said bump pad area.
The method further comprises the step of forming a second polymer layer on the first polymer layer and the redistribution patterns; removing a portion of the second polymer layer to expose at least a portion of the bump pad areas; forming a second barrier metal layer on the bump pads areas; and forming a solder bump on each of the bump pads areas.
In accordance with the present invention, wherein the concave pattern is formed in each bump pad area simultaneously with forming the redistribution pattern.
REFERENCES:
patent: 5736456 (1998-04-01), Akram
patent: 6218281 (2001-04-01), Watanabe et al.
patent: 6287893 (2001-09-01), Elenius et al.
patent: 6400021 (2002-06-01), Cho
patent: 6449838 (2002-09-01), Murakami
patent: 63076339 (1988-04-01), None
Ezawa et al., Eutectic Sn-Ag Solder Bump Process for ULSI Flip Chip Technology, IEEE Transactions on Electronic Packaging Manufacturing, vol. 24, No. 4, Oct. 2001, pp. 275-281.
Hwang Chan Seung
Jung Seung Ouk
Harness & Dickey & Pierce P.L.C.
Pham Long
Trinh Hoa B.
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